Cyclone 10 LP JTAG galvanic isolation

[JanVrkoslav]

Hello,

Cyclone 10 design guideline says:

JTAG pins in the Intel Cyclone 10 LP device are powered up by VCCIO. However, you
may need to use VCCA in some cases.
• For devices using VCCIO of 2.5, 3.0, and 3.3 V, all I/O inputs must maintain a
maximum AC voltage of 4.1 V because JTAG pins do not have the internal PCI
clamping diodes to prevent voltage overshoot. You must power up the VCC of the
download cable with a 2.5-V supply from VCCA.

I have to ensure that voltage on the JTAG pins is not above 4,1V.  My VCCIO is 3,3V.

In my case is implemented galvanic isolation on the board. (FPGA -> Isolator -> USB blaster).

Iam sure that 3,3V power rail on my board will not exceed 3,5V. 

And the question is: Do I have to use voltage level shifter between FPGA and ISOLATOR for TDO, TCK and TMS pins from 3,3V to 2,5V?

Thanks!

[FvM]

Your JTAG interface signals are sourced on board, thus it's quite simple to avoid overshoot that might violate input voltage range. I would add source side series termination with trace impedance (e.g. 50 to 70 ohm, including driver impedance).

Frank  

[JanVrkoslav]

Hi, 

thanks for reply. In GPIO handbook is written that Dedicated configuration pins and JTAG pins do not support impedance matching or
series termination.

But I was asking why I MUST power up the device with 2,5V if Iam sure that my power rail will not exceed 4,1V. Thats possible issue of the USB blaster? Can I proceed with 3,3V levels or not?

Thanks

Jan

[YuanLi_S_Intel]

Hi Jan

It is recommended value from the datasheet. You can try with the other voltage with level shifter. However, user need to take the risk from using that.