Cyclone 10GX default register state on power up

[designEngineer]

What is the default register sate for Cyclone 10GX devices on power up?

I found in the core fabric and general i/o handbook that MLABs power up cleared but can't find anything about regular ALM registers.

I also found that the DEV_CLRn pin can reset all registers in the device but I need to know if registers come up cleared on power up without using that pin.

The background for that question is about handling the reset for the design after programming. If only a clock is provided from the outside, I would like to have a counter count up to a certain value at which the internal reset gets released and everything starts up. For that to work I need to know that the counter registers are coming up cleared.

If the registers generally are not coming up cleared on power up, is there a way to set a power up default value to specific registers in the RTL? For example, would:

logic [23:0] reset_cnt = 'd0;

synthesize to a design that defaults those registers to 0 on power up?

Thank you!

[sstrell · Accepted solution]

All registers power up low.  Memories can be initialized with a memory initialization file (.mif or .hex), but initially at power on, everything is low.

[designEngineer]

Thanks for the reply. Is this stated in any datasheet, user guide or any other official documentation?

[EngWei_O_Intel]

Hi 

You can refer to the link below:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd12091999_3143.html

Thanks.

Eng Wei

[sstrell]

In a number of the device documentation but specifically page 44 here:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an801.pdf