I designed a board with high speed adc,dac and clock on an fmc board to match with the fmc connector on the cyclone 10gx eval board. For the most part it is working good. I am running into an issue with serdes. I overlooked this part when assigning the pins that when using serdes, the clock and all the data lines need to go to the same bank. I missed this part and clock and most of the data lines are routed to bank 3A. Two of the data lines are routed to bank 3B. I am going to do another version of the board to route all the signals to bank 3A. Is there a way, I can test the other data lines for functionality in the mean time? would it be possible to use manual deserialization or a way to bypass the constraint that all the data lines need to go to the same bank? this is only temporary and I would like to test these lines, before another revision if possible. Please let me know
thanks for the reply. I tried the following as per your suggestion
reference clock going to two different banks and two plls
one bank refclk->pll0->serdes(with 7 channels)
second bank refclk->pll1->serdes(with 2 channels)
and added the set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to <name of toplevel reference clock input port> in the qsf file
the compiler failed at the placement stage, reason being fitter can't place logic LVDS_CLOCK_TREE that is part of LVDS SERDES INTEL FPGA IP
it almost looks like, I won't be able to test this withe the existing set up. please let me know, if I can add any other constraints to bypass it
Hello Ramakrishna ,
Just curious ; Did you manage to find this issue you facing ? i am not sure i know anymore constraint ? Also let me know how i can help you further for the same ?
Thank you .