I am using Cyclone 10LP device in one of the application for reading input frequency signal of 5kHz to 15kHz.
Input signal is connected to two IOs pins of Cyclone 10LP device directly.
a sample code is written to read input frequency.
the code is working fine when we power-on cyclone 10lp first and later power-on input frequency signal.
when we power on input signal first and power On cyclone 10lp, cyl 10LP is not able to detect the input frequency signal.
to over come this again we have to do power on cycle or
reprogram the cyclone 10LP (if we reprogram cyclone 10LP the input signal start reading correctly)
this even we tried by changing two other IO pins also. the problem remains same.
unable to monitor using signal tapping tool also, since in signal tapping we need to reprogram every time to monitor any of the signal, so reprogramming will not detect the problem.
let me know if any of the sitting needs to change in the device or suggest the solution for the problem.
Can you provide any code? That would be helpful.
Is the design meeting timing requirements? You're talking about kHz signals but it would still be useful to see what timing constraints you are using for your design.
As far as Signal Tap is concerned, when you say you are "unable to monitor", what exactly is happening with the tool that is not working as you expect? What are you using as the trigger for the tool?
For reading khz signal, we are using 25MHz as system input clock frequency and internally generating 160MHz using PLL.
Timing constraints are not design for this code, since the code is working fine. when input signal will power-on after some delay.
using signal tapping we are trying to monitor power-up problem and trying to monitor the each stage probing. since the problem is not able to recall it because of reprogramming of FPGA, when we reprogram FPGA it will start working/reading frequency.
"Timing constraints are not design for this code, since the code is working fine."
It doesn't matter if the design seems to be working fine. You *always* need to constrain a design with timing constraints in a .sdc file. Without it, there is no guarantee that anything output by the Fitter will always meet your timing requirements.
For Signal Tap, if you're trying to debug something that is happening just after programming the device, you can try using the power-up trigger feature. This will cause the logic analyzer to automatically start looking for one or more triggers immediately after device configuration but before you're able to start the logic analyzer in the .stp file. If the trigger occurs, the captured data is stored in the logic analyzer memory buffer and automatically transferred to the .stp file when you first start the logic analyzer. See the documentation for details on power-up trigger.
Thanks for your support,
i just shorted input signal to one of the test point(TP),
i found that input signal is not able to detect by C10LP at power-on state, i.e. their is no signal at the TP. when i reprogrammed by JTAG/power off complete set-up and power-on C10LP first and later input signal, C10LP can able to detect,i.e. signal at the TP same as the input signal.
In Pin planner this pin is declared as 3.3V_LVTTL, their are no modifications in assignment editor.
can you suggest some of the settings in quartus prime that how to detect the signal.