Cyclone 3 Not entering AS Mode

[Kodion22]

Before i start, will love to say am new to FPGA and entry level with Electrical. 

We have an old tool we purchase that has a Cyclone 3 board on it. We have a simple code (attached) that we can easily run through JTAG with no issue.

When we try to run as AS we get some error about invalid device. We load the code to the EPCQ16A memory chip using a tool and when we put it back, it still not running. We probed the DCLK of the Cyclone and signal is at 17khz and very noisy. 

Spent weeks on this with zero support. Please can someone tell us what we are missing here?

[sstrell]

Without knowing the hardware setup of the board (is it a dev kit or custom?) or seeing the original project (this is just a programming file you've attached instead of the Quartus project), it's going to be difficult for anybody to help you out.  If it's a dev kit, mention which one it is.  If it's custom, provide schematics to see the connection and setup between the device and the flash.

[Kodion22]

Thanks @sstrell  for the response. Attached is my circuit. A bit of a history. Circuit was a built a while back and it was working. Circuit was built again recently and the issue started and we don't where to start. Pad is grounded and we have all the Pull up and Pull downs. we built multiple and still having the issue. Not sure if there is something we need to do to put the circuit on AS mode. From what we can see, it is not getting into AS mode

[sstrell]

Your post here says you're using an EPCQ16A, but your schematic says you're using a much older EPCS16.  Have you just created the programming file for the wrong device?

[Kodion22]

Since EPCS is not available anymore, we switch to EPCQ16 which is supposed to be compactible. Even without using the memory chip, it seems like we are not getting any clock from DCLK which from reading the documentation will not have anything to do with the memory chip we are using. We are just trying to run a simple programming file that outputs frequency so that we can see it in TX to verify that things are well. Also we cant program AS at all. 

[sstrell]

If you're not seeing the 30 or 40 MHz output on DCLK, maybe the device is damaged, causing a problem with the internal oscillator that drives DCLK.  Is this a single board or happening on multiples?

[Kodion22]

Thanks for the swift response. I have manufactured 4 boards and the same thing. I have purchased multiple cyclone 3 chips and they all behave same way. Am able to connect via jtag with no issues but can never connect AS or if I load .pof code externally on the memory chip, it doesn't seem to be running. Also, the DCLK is not showing 30 to 40mhz.

Is the chip supposed to be showing that constant 30-40mhz on DCLK? If not, can any other external thing be a factor? Lime capacitor or resistors. I just don't understand the natural behavior of this FPGA

[sstrell]

You probably need to be going though the handbook and check things like power supplies, pull-ups and pull-downs, etc.  Something is not right. 

https://www.intel.com/content/www/us/en/content-details/654357/cyclone-iii-device-handbook.html

[Kodion22]

I went through the document and went through all my voltage levels and everything is perfect going into the FPGA. All my pull ups and pull downs are good. At this point I don't want am missing. I was having an issue with jtag and I grounded the pad. That took care of it. Now I simply want to know what else can affect the DCLK from oscillating at 30 to 40 MHz

[Kodion22]

From what I read, if that happens it can trigger the EPCQ/EPCS chip to send data to the clyclone

[FvM]

Hi,
I think some details of the error report are still unclear. What's meant e.g. with "I was having an issue with jtag and I grounded the pad." Grounded which pad?

I generally agree with sstrell that i looks much like a problem of correct PCB wiring and signal integrity.

Not sure if the FPGA relatic schematic part is shown completely. I'm missing e.g. JTAG pull-up/-down resistors. Particularly missing 1k TCK pull-down can cause erratic operation of JTAG logic and e.g. block AS configuration.  The schematic shows about no supply bypass capacitors, this can cause serious issues depending on PCB layout. But I won't finally assess possible power and signal integrity problems without seeing full schematic and layout.

First step of AS circuit test is successful JTAG indirect flash programming and verification. If this doesn't work, it's rather unlikely to get AS configuration loaded.

A specific question was about DCLK operation. DCLK is driven by the FPGA during AS configuration. In addition, Intel AS programming IP (e.g. ASMI) is sending continuous DCLK. Unless you instantiate respective IP in your design, DCLK shoul be quiet in user mode.

Regards
Frank

[Kodion22]

I am able to program the FPGA via JTAG. I can successfully upload code with no issue. My issue right now is getting AS to work. I do have the AS pin for the blaster but when i connect my blaster to it, i get error about silicon id. From what all i can read, it seems like the FPGA is not going to AS mode. Am not sure what all can cause it.

Ground pad means, putting a wire through the ground pad of my Cyclone and connect it to ground.

More insight.. The circuit was built in 2007 and it has been working. We did a latest redesign to be able to use newer components. So basically i want to gain the knowledge to troubleshoot better since am not certain is from the circuit since this has been working for years on the older boards

What frequency should i get on my DCLK pin when the board is plug up and the memory chip is on the board? I believe there should be continues clock even when you are not doing any AS programming in Quartus. Nowadays some people can load code into the memory chip using a tool and solder it into the board. So if the memory chip has the program, wouldn't the FPGA pick it up via the DATA pin?

Again, am new to all this. So pardon me if am not using the right words

[Farabi]

Hello,

Could you please provide the scopeshot for below signals?

1. nCONFIG
2. CONF_DONE
3. nSTATUS
4. VCC (during ramp up)

all with the same timeframe. We can check what stage the device fail and troubleshoot from there.

regards,

Farabi

[Kodion22]

Apologize.. I have been sick and haven't been to the lab. Am going to collect some scope today on it and paste some of it on here.

[Kodion22]

Here is what am getting when i probe the pins

Here are the pins on the resistors

[Kodion22]

Please can someone help me with this issue? I have been stuck on this for over 2 months now. According to the documentation, Cyclone 3 family should always oscillate on DCLK at least 40MHZ. Am barely getting 700khz. I have bought multiple cyclone chips and changed and still no difference. How do i trigger the internal oscillator? 

[FvM]

Hi,
you wrote recently: "According to the documentation, Cyclone 3 family should always oscillate on DCLK at least 40MHZ. Am barely getting 700khz."
DCLK is not generally oscillating in Cyclone III AS configuration. Which document are you referring to?
DCLK is operating during configuration load and stops after starting user mode, except for a special case mentioned above.
Presumed the AS flash is correctly connected to FPGA and configuration mode set to AS, the flash can be programmed and verified in JTAG indirect mode.

[Kodion22]

I hope am not misunderstanding the documentation. Here is the reference attached. I also attached the screenshot. Also i have an old evulation board and when i probe the DCLK it is about 40MHZ. It is also a cyclone 3 but a different family than mine.

what do you mean by Presumed the AS flash is correctly connected to FPGA and configuration mode set to AS, the flash can be programmed and verified in JTAG indirect mode"

[FvM]

Hi,
the handbook quote talks about expectable DCLK frequency when operting, not about continuous clock. During initial configuration load, DCLK isn't running continuously. The "old evaluation board" has possibly SFL IP compiled into the design, special case discussed above.

JTAG indirect programming uses figure 9-30 according to Cyclone III handbook.

[Fakhrul]

Hi Kodion22,

Any updates on this issue? Based on your previous statement that no problems occurs on the older boards, it is highly due to the isssue with a new board's design. Could you identify the key changes between the old and the new boards?

Regards,

Fakhrul

[Fakhrul]

As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Intel experts. Otherwise, community users will continue to assist you here. Thank you.