Cyclone 5 mismatch between VCCPD and VCCIO

[Altera_Forum]

We created a custom board that has 5CSEBA4U19 chip. The VCCPD pins for all banks have 3.3V but VCCIO is 2.5 on some banks. 

The datasheet clearly states that I must  set VCCPD to 3.3V when VCCIO is 3.3V set VCCPD to 3.0V when VCCIO is 3.0V set VCCPD to 2.5V when VCCIO is 2.5V or less  but my problem is that I set the VCCPD to be 3.3V while VCCIO is 2.5V. Will this be a huge problem? The other problem is that I set the VCCIO of bank3A to be 2.5V although it contains the pins for the JTAG and EPCQ connections, VCCPGM is 3.3 and EPCQ has 3.3V supply. Will this be a problem?  Thanks

[Altera_Forum]

All that can be said for certain is that the board does not follow the requirements of Altera's datasheet. Unfortunately, the board is wrong. 

   --- Quote Start ---  Will this be a huge problem?  --- Quote End ---  Does it matter? Only Altera can tell you what to expect. I suspect the FPGA will work, or appear to work, fine - but for how long...  As for connecting your 3.3V powered EPCS to a 2.5V bank - this is not likely to be an issue under any lab conditions, but may not work over all voltages and temperatures. Driving into the FPGA at 3.3V levels will be fine. However, if the 2.5V signal from the FPGA drops a little (but within the FPGA's spec) it may well be below the minimum threshold specified on the datasheet for the EPCS for a valid logic high. So, conceivably the EPCS could stop working even though the 2.5V output signals from the FPGA remain in spec. (You can check all this by looking at the datasheets for the FPGA and EPCS.)  Cheers, Alex

[Altera_Forum]

Hi, 

 Device will operated in recommencement condition only. Board may work or may face drive strength issues.  Check the table:14 in the linkhttps://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_51002.pdf and check the Fig 2:https://www.altera.com/support/support-resources/operation-and-testing/power/pow-overview.html 1.You have set VCCPD to 3.3 Volt and VCCIO=2.5 Volt which will have direct relation with input and output voltages(Vil,Vih,Vol & Voh). According to your setup VVPD supply will have different range of Vil,Vih,Vol & Voh values and VCCIO will have another ranges. You may not able drive logic high when pin is output & logic low when input.  Now if output of level shifter is high, you can drive predriver input only if you have voltage greater than 2.2V (vihmin of predriver block). so driving wise there may be issues.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

Thank you all for your replies 

   --- Quote Start ---  All that can be said for certain is that the board does not follow the requirements of Altera's datasheet. Unfortunately, the board is wrong.  Does it matter? Only Altera can tell you what to expect. I suspect the FPGA will work, or appear to work, fine - but for how long...  As for connecting your 3.3V powered EPCS to a 2.5V bank - this is not likely to be an issue under any lab conditions, but may not work over all voltages and temperatures. Driving into the FPGA at 3.3V levels will be fine. However, if the 2.5V signal from the FPGA drops a little (but within the FPGA's spec) it may well be below the minimum threshold specified on the datasheet for the EPCS for a valid logic high. So, conceivably the EPCS could stop working even though the 2.5V output signals from the FPGA remain in spec. (You can check all this by looking at the datasheets for the FPGA and EPCS.)  Cheers, Alex  --- Quote End ---    Won't the FPGA bank that has 2.5V VCCIO and is connected to the 3.3V EPCS get damaged because of this supply mismatch?

[Altera_Forum]

--- Quote Start ---  Hi,  Device will operated in recommencement condition only. Board may work or may face drive strength issues.  Check the table:14 in the linkhttps://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_51002.pdf and check the Fig 2:https://www.altera.com/support/support-resources/operation-and-testing/power/pow-overview.html 1.You have set VCCPD to 3.3 Volt and VCCIO=2.5 Volt which will have direct relation with input and output voltages(Vil,Vih,Vol & Voh). According to your setup VVPD supply will have different range of Vil,Vih,Vol & Voh values and VCCIO will have another ranges. You may not able drive logic high when pin is output & logic low when input.  Now if output of level shifter is high, you can drive predriver input only if you have voltage greater than 2.2V (vihmin of predriver block). so driving wise there may be issues.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)  --- Quote End ---    If there is an input signal to this bank, it will be 2.5V not less and I hope it gets detected by the FPGA. The problem is I have LVDS TX and RX pins on those banks (the banks that have 2.5V VCCIO but 3.3V (or 3V) VCCPD).  I think I am gonna try and assemble one board and test. Thanks

[Altera_Forum]

--- Quote Start ---  Won't the FPGA bank that has 2.5V VCCIO and is connected to the 3.3V EPCS get damaged because of this supply mismatch?  --- Quote End ---  No. Refer to table 2 in the "cyclone v device datasheet (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_51002.pdf)". This specifies the maximum operating overshoot the device can sustain before damage occurs to the device. Note: nowhere in this table does it specify how any of the rails are powered - it's independent of that.  If you're happy to assemble a board I'd suggest you will be able to do a lot with it. So, it will not be wasted.  All that can be said about input/output voltages, pre-drive behaviour and drive strength is that your setup is not supported, therefore not documented. However, as I've already suggested, a lot, if not all, of your board should work.  Cheers, Alex

[Altera_Forum]

Thank you a_x_h_75. 

After I finish the board and test it I will reply here in this thread with my results.