Cyclone III JTAG and AS Configuration

[Altera_Forum]

Problem: 

I am receiving the conf_done pin failed to go high error when trying to program using the JTAG interface.  Background: I have configured a custom board to use both AS and JTAG configuration schemes. I used Figure 9-29 in the Cyclone III handbook as my reference.   I set the MSEL pins to 010 for Fast Active Serial Standard (AS Standard POR).  I am able to successfully program the Cyclone III using the AS mode with an EPCS16. Therefore I feel confident that the FPGA is installed properly and is not damaged.   I have verified using a scope that the conf_done line doesn't get pulled up during JTAG configuration. It never even moves so I don't think that it is a timing event that is getting missed.   I have attached the FPGA Configuration portion of my schematic for review.   I know that there are a lot of posts on this topic, but I haven't found a solution yet that has solved my problem.   Any assistance that anyone can provide will be greatly appreciated.  Thank You

[Altera_Forum]

Except for the nCE connection of JTAG connector pin 6, which is not according to Altera suggestions, everything seems correct. Driving nCE high during JTAG configuration attempt makes it fail. Possibly, the Quartus programmer just does this.

[Altera_Forum]

Thank you FvM. I disconnected pin 6 of the JTAG connector and was able to successfully program.  

 I got confused when reading note 3 on Figure 9-29 from the Cyclone III Configuration Guidebook.  Quoted Text in Red (3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO must match the VCCA of the device. For this value, refer to the MasterBlaster Serial/USB Communications Cable User Guide. In ByteBlasterMV, this pin is a no connect. In USB-Blaster and ByteBlaster II, this pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.  Since I am using a USB-Blaster and wanted AS support on my board I thought that the last sentence of the note was applicable and connected nCE to pin 6.   Does that note apply if I was going to use the JTAG port to program the EPCS device using the Serial Flash Loader?   Thank you again for your assistance!

[Altera_Forum]

No, the nCE pin has two purposes:  

- Tri-Stating the FPGA pins connected to configuration memory, when programming it by an external circuit, e.g. the AS connector. - Disabling the configuration controller in multi-FPGA schemes. As a side effect, JTAG configuration is blocked as well.  The text referring to nCE in the JTAG connector description is somewhat misleading in my opinion. It's actually describing the fact, that pin 6 is used different between older and newer Altera programming adapters. Some older adapters expect pin 6 connected to a supply voltage reference, but it can be unconnected for USB or Byte Blaster.

[Altera_Forum]

FvM, 

 Thank you for the clarification on the note. It makes a lot more sense now.   I really appreciate your quick responses to my posts.