Cyclone III PLL cascading - lack of information

[Altera_Forum]

Hi everyone! 

I try to run a Design with two PLLs. The first one not reconfigurable, inclk from dedicated clock pin (100MHz), located in PLL1. The second one is reconfigurable, inclk from the first one (100MHz) via global clock network, located in PLL3. The first PLL works fine. The second one should output a clock signal to a general purpose IO Pin, but it doesn't!  I synthesized the design only using the reconfigurable PLL, directly fed from the dedicated clock pin. This works. So I'm sure, all inputs to the PLL entity (for reconfiguration and stuff) are connected correctly and the mif file for initial configuration is fine too.  PLL related warnings I get when I synthesize the version with both PLLs are: - The input ports of the PLL <first PLL and 2nd PLL> are mismatched, preventing the PLLs to be merged --> This is ok I guess, because I don't want them to be merged. - PLL <reconfigurable PLL> input clock inclk[0] may have reduced jitter performance because it is fed by a non-dedicated input - PLL <reconfigurable PLL> output port clk[0] feeds output pin "test1~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance --> Not nice, but I think both should not lead to NO output signal.  (The device is an EP3C16Q240C8)  Any ideas? I would be happy about every hint! Nor the Cyclone handbook neither an application note could help me so far. Thanks in advance!

[Altera_Forum]

No ideas? :(

[Altera_Forum]

Cascading PLLs works in Cyclone III without problems, you get the said "jitter" warning however. If you see no output, something else must be expected wrong in your design. You may want to check the compilation report regarding PLL thoroughly, if it understood your intended configuration.

[Altera_Forum]

maybe you can try running the line between the PLL through clock buffer, that way the input to the second PLL might be considered as a dedicated line.

[Altera_Forum]

Finally... it works! 

The only thing I had to do is to change the location of the reconfiguarable PLL from PLL 3 to PLL 2. This is reproducible. I did not use PLL specific stuff like differential clock output ports or such things. There is only one PLL output connected with a GPIO. So I wonder why the location of the PLL has an influence on the synthesis result.

[Altera_Forum]

How is it possible to select a PLL? (Changing from PLL2 to PLL3)

[Altera_Forum]

--- Quote Start ---  How is it possible to select a PLL? (Changing from PLL2 to PLL3)  --- Quote End ---    Open the assignment editor in Quartus II by right clicking the PLL and select Locate in assignment editor.  In category: select PLL In the lower part you can select the Loaction. (see attached jpg-file)  Good luck, Ton

[Altera_Forum]

Hi Ton, thank you for the hint. But I can't find the option "PLL" in Category in Quartus 9.1 SP2. Do you have an idea? I can see a similar option called "Locations" but it isn't possible to select a PLL. Du you have an idea? 

 BR, Carsten

[Altera_Forum]

Hi Carsten, 

 I don't get it. When I unfold "category", I see PLL, amongst others (see picture).  Did you already assign a device? Because if no device is assigned, the location could not be determined.  Regards, Ton