Cyclone III Reset with unrelated HV pulses

[Altera_Forum]

Hi All, 

 I have a cyclone III that I am using to filter and process a digitized waveform created from an attenuated high voltage source on the same board. The board takes in up to 15kV and attenuates it down to <1V for digitization by an ADC, where the signals are sent to the CIII and filtered and processed for export to a microcontroller. The design works fine at lower analog input pulses, up to ~4kV, however above this point my FPGA seems to go into configuration mode and all of my outputs go high (I imagine they are being tristated and then the pull-up resistors bring the signals up to my 3.3V). Can anyone give me some guidance as to what circumstances would put my FPGA back into configuration mode? When I bring the input pulses back down to below the ~4kV threshold the EPCS4 reconfigures my FPGA and it works fine again.   Thanks for any help!

[Altera_Forum]

--- Quote Start ---   Can anyone give me some guidance as to what circumstances would put my FPGA back into configuration mode?   --- Quote End ---   An FPGA will go into configuration mode if you pulse the nCONFIG pin, or nSTATUS, and possibly CONF_DONE. Check those signals for coupled noise.  The FPGA has a power-on-reset circuit too ... though I'm not sure that it is active after an FPGA has configured ... you could check that the power supply voltages all look clean too.  Cheers, Dave

[Altera_Forum]

We had a board quite some time ago, whose make up sounds similar, that suffered similar problems. For cost reasons we had our high tension circuitry on the same board as the FPGA - albeit a FLEX10K device. The device repeatedly lost it's configuration depending on the high tension input signal. 

 After much investigation we separated the circuitry over two boards, added more filtering and yet more protection and the problem went away.  The only explanation offered at the time was RF interference - something that never sat very well with me - but who was I to say 'absolutely not'. The only additional evidence to defend my stance was, no matter how close we placed the two boards in our new solution, we never saw the FPGA lose it's configuration.  Cheers, Alex