Cyclone III and 400 Msps DAC

[Altera_Forum]

I want to drive a 400 Msps DAC (DAC5675A) with EP3C16Q240C8. The FPGA 's PLL cannot create a 400 MHz clock for the DAC due to hardware constraints, although it can produce 400Mps LVDS DATA thanks to dedicated DDIO ciruit. Is an external clock-distribution chip necessary to clock the DAC? Would this require external PLL usage along with the ALTLVDS Tx? Thank you.

[Altera_Forum]

Yes, the C8 output toggle rate is limited to 320 MHz. So you need an external clock doubler circuit. Using a faster (C6 + BGA package) CIII version may be the more simple solution. The 200 MHz LVDS clock can be still generated from an internal PLL in my opinion. A fine tuning of LVDS versus external 200 MHz clock phase is most likely necessary, but basically a simple action.

[Altera_Forum]

FVM, thanks for your really quick reply. 

 Actually i m thinking of using the ALTLVDS Megafunction along with an "external" PLL (ALTPLL Megafunction) to clock the data. That PLL can provide slow and fast clocks for the Tx and also the reference clk for the distribution chip so that LVDS Data and CLK can be synchronized for the DAC. The thing is, that theres is also an SRAM chip that feeds the slow data to the ALTLVDS Tx, and this chip has to be clocked too, so maybe that Megafuncion PLL can also take care of that (200MHz) CLK needed there. Is synchronization of all this clocks possible? Changing the FPGA is not really possible for many reasons. Thanks a lot    P.S: While the PLL can create output clocks of at most 300 MHz, when editing the output clock frequency value of the Megafunction, the "Able to implement the requested PLL" Message appears even for values of 600 or 900 MHz. Of course, during simulation Quartus warns that these frequencies cannot be implemented. Is it some kind of bug?

[Altera_Forum]

I didn't get the meaning of "External PLL" in your post, because I'm using mostly "external" PLLs resepectively custom LVDS transmitters with Cyclone family. Yes, the LVDS function needs 2 different clocks, so the PLL has 3 clock outputs available for other purposes. Even a combination of two cascaded PLL's can work, but it would involve higher clock uncertainty. 

 Just for fun, you can evaluate the actual maximum toggle rate of your FPGA by faking a EP3C16xxxC6 chip.

[Altera_Forum]

I'm planning to use a separate clock generation chip in order to create the 400 MHz clock required by the DAC. The tx_outclock provided by the FPGA PLL should be the Reference CLK for this purpose. I also think I' ll have to use the "PLL LOCK" output pin of the external chip as a latch enable for the LVDS Data Transmission. The question is, how am I going to synchronize the LVDS Data with the Clock, so as the DAC will sample them properly? Should I try the “Specify phase alignment of ‘tx_outclock’ with respect to ‘tx_out’” option of the ALTLVDS Megafunction? . Any ideas are welcome, 

  thank you in advance!  

[Altera_Forum]

Yes, this should work. You can output a testpattern, determine the clock phase limits, that still achieve correct DAC output and set the phase shift to the mean value.

[Altera_Forum]

I ll try it ty :)