This took me about 1.5 days to figure out, so I am posting this in case it helps someone else.
My design has a single EP3C16 device. The nCE pin is driven by an external ARM9 GPIO (for reasons I will not elaborate on here). I discovered a behavioral anomoly that occurs when nSTATUS transitions to logic 0, followed by nCE transition to logic 0. Specifically, the FPGA's nCE pin will begin to source significant current and thus exceed the ARM's ability to drive nCE to logic 0 (resulting in a "logic 0" level of roughly 800mV).
Interestingly, this does not happen immediately when nCE switches to logic 0; it happens approximately 40 to 50 milliseconds later! When ARM drives nCE low, it does go to nominal 0V initially, then the high current starts 40-50ms later. Once this happens, other signals will behave strangely as well, as if some sort of internal FPGA latch-up has occurred. Cycling power is the only way to clear the problem and restore normal operation to the FPGA.
Moral of this story: if you are actively driving nCE, make sure nCONFIG is held at logic 1 when nCE goes active.
