Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18968 Discussions

Cyclone III programming problem (JTAG and AS)

Altera_Forum
Honored Contributor II
1,994 Views

Hello All, 

Please help! We have a problem with Cyclone III devices programming. We are using the board with 5 Cyclone III devices, connected in Combining JTAG and Serial (ESPC64) configuration. Figure 7-5 in Configuration Handbook and Figure 9-5 in Cyclone III device handbook. Bad things - it was errors in PCB layout, especially in configuration of MSEL pins on all FPGAs. And no way to fix it.  

Now the question. Do we have chance to program FPGAs without AS configuration device?:confused:  

Appresuated for any help.
0 Kudos
30 Replies
Altera_Forum
Honored Contributor II
452 Views

What's the actual MSEL configuration? 

How did you connect the JTAG interface(s)?
Altera_Forum
Honored Contributor II
452 Views

Thanks for replay, FvM. 

Actual MSEL configurations are Active Parallel (3.3V) for Master and Fast Passive Parallel Fast (3.3V) for next 4 slaves. Which was good for previous revision with parallel configuration. JTAG is configured in chain, as I mention before, Figure 9-26 in Chapter 9, Cyclone III Device Handbook, Vol 1. And, it sims to be JTAG is working. Autodetect in programmer showing a correct configuration and I'm able to configure the serial configuration device (EPCS64) by JTAG, as well as by AS Interface.  

The board is high density 16 layers board, as well as very expencive and I would like to debug other circuits on the board before next revision, what I can't do without programmed FPGAs. So, I will really appresiate for any help and ready to submit any information which can help.
Altera_Forum
Honored Contributor II
452 Views

Hello, 

 

I have built a board which has an Altera cyclone IV device (EP4CE10E22C8N). I want to configure FPGA using FTDI (FT2232HL) in JTAG mode. I am having difficulty as my board is not getting detected. 

 

I am using UrJTAG to communicate with the Cyclone IV device. And EPCS4 as the serial memory. 

 

An error is seen when I hit the detect command in UrJtag i.e. tdo seems to be stuck at 0 

 

All the necessary connection as mentioned in Altera Cyclone IV datasheet.  

Please let me know if u have any idea where and what am I doing wrong.  

 

Regards, 

 

Saurabh
Altera_Forum
Honored Contributor II
451 Views

hello  

 

i am also using cyclone IV device and i am trying to configure my FPGA in jtag mode. 

 

i am using FT2232HL for USB to JTAG protocol conversion. 

 

but when i try to detect my device in UrJTAG console i an receiving a Warning saying 

 

TDO seems to be stuck a 0. 

 

i have checked all my connections 10 times, they all are as per the cyclone IV design guide and Pin connection guidelines provided by altera. 

 

to be more specific here are the connection I made for the jtag mode of configurations. 

 

Altera devices use the four JTAG pins for JTAG programming or configuration. They should be connected as below: 

 

  1. TCK (Test Clock) - From download cable in parallel to every device in the JTAG chain. Weakly pulled-down to GND. Check the Configuration Handbook or specific device Handbook for resistor values. 

  2. TMS (Test Mode Select) - From download cable in parallel to every device in the JTAG chain. Weakly pulled-up to VCCIO. Check the Configuration Handbook or specific device Handbook for resistor values. 

  3. TDO (Test Data Out) - The TDO pin of a device is connected to the TDI pin of the subsequent device in the JTAG chain. For the last device in the JTAG chain, the TDO pin is connected to the TDO pin of the download cable. 

  4. TDI (Test Data In) - TDI pin of a device is connected to the TDO pin of the preceding device in the JTAG chain. For the first device in the JTAG chain, the TDI pin is connected to the TDI pin of the download cable. 

 

Even though other programming or configuration pins (for FPGA) are not used in JTAG mode, they must be properly connected and cannot be left floating. 

 

  1. nTRST - Driven high during JTAG configuration. 

  2. nCE - Connect to GND or driven low during JTAG configuration. 

  3. MSEL pins - Connect to ground. 

  4. nCONFIG - Driven high or pulled to VCC through a pull-up resistor. 

  5. DCLK - Either pull-up or pull-down through resistor. 

  6. DATA pin(s) - Either pull-up or pull-down through resistor. 

  7. nSTATUS - Pull to VCC through a pull-up resistor. When the device is powered-up, this pin will be released to high. 

  8. CONF_DONE - Pull to VCC through a pull-up resistor. Should be pulled-up individually for the devices in a chain. When the device is successfully configured, this pin will be released to high. 

  9. INIT_DONE - When used, pull-up to VCC. 

 

 

 

 

i have also give the path for the bsdl file in UrJTAG shell.  

 

i am not able to figure out what is the problem and why is my FPGA not getting detected. 

 

please let me know if you have any idea as yours design seems to work with cpld and fpga. 

 

Regards 

 

Saurabh Agrawal
Altera_Forum
Honored Contributor II
451 Views

 

--- Quote Start ---  

 

please let me know if you have any idea as yours design seems to work with cpld and fpga. 

 

--- Quote End ---  

 

 

You can try resetting the JTAG chain and the toggle TCK and assert TMS to bring the JTAG TAP into the Shift-DR sequence. The default contents of the DR register are the device ID code. Toggle TCK 32 times, and probe TDO. It should toggle - on all device outputs. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor II
452 Views

Thanks for the quick response.. 

 

please can you elaborate a little more..
Altera_Forum
Honored Contributor II
452 Views

 

--- Quote Start ---  

 

please can you elaborate a little more.. 

--- Quote End ---  

 

 

The JTAG TAP machine is on page 10 

 

http://www.altera.com/literature/ug/ug_virtualjtag.pdf 

 

If you hold TMS high and clock TCK 5 times, then you will end up in the TAP reset state (TEST_LOGIC_RESET). The device IDCODE will be loaded into the DR register. 

 

If you clock in the TMS code 0, 1, 0, 0, you will be in the SHIFT_DR state. 

 

Hold TMS low and pulse TCK for 32 clocks and IDCODE will be shifted out on the TDO pin. 

 

Put the TAP back in reset, and repeat.  

 

You should then have a data stream on every TDO pin on your board. 

 

If you don't, then your JTAG chain is broken. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor II
452 Views

Hey, 

 

Is there some sort of emulator or logic analyzer that is to be used for all that you suggested. 

 

I am find a hard time figuring out that how am I suppose to this???? 

 

My PCB is ready and soldered. I have made all connections as per the altera design guide. 

 

Why is this neccesary and do I have to repeat this for all my fpga design using cyclone 4 in jtag configuration mode. 

 

Thanks, 

Saurabh
Altera_Forum
Honored Contributor II
452 Views

 

--- Quote Start ---  

 

Is there some sort of emulator or logic analyzer that is to be used for all that you suggested. 

 

--- Quote End ---  

The Altera USB-Blaster and Parallel Port ByteBlasters can be used, a digital I/O board, a microcontroller board, etc. 

 

Altera's Quartus tool has a JTAG debugger. It probably does the above sequence too. 

 

 

--- Quote Start ---  

 

I am find a hard time figuring out that how am I suppose to this???? 

 

--- Quote End ---  

Figuring stuff out like this makes you an engineer. So get to work! 

 

 

--- Quote Start ---  

 

Why is this neccesary ... 

 

--- Quote End ---  

Because you said TDO was stuck at ground, and you wanted help to figure out why. 

 

If the JTAG chain on your board works, and you can configure your device via JTAG, then of course you do not need to do any of this, since your design is working. Then you would move onto confirming that AS configuration mode works. 

 

Don't get scared off by one failure. Its fixing the problems that is the fun part. If stuff always worked, you'd never really learn how to debug problems would you? :) 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor II
452 Views

Hey Dave 

 

I was just trying to find out more solutions.  

 

and I just read that there is a grounding pad exactly at the center of the IC 

which has to be ground other wise the device wont work.  

 

but while creating the footprint of my TQFP 144 EP4CE10E22 there was not grounding pad present. 

 

do you think this might be a reason of the device not getting detected. 

 

And Cheers I will make it work!!! :)
Altera_Forum
Honored Contributor II
452 Views

Yes, if the exposed pad isn't connected to ground, the JTAG doesn't work. You need to connect it to ground. Some people managed to do this on a soldered board by carefully drilling the PCB under the FPGA and soldering a wire from the pad to ground.

Vasudev
Beginner
242 Views

Hi,

 

I am facing a similar problem where I always get the error "JTAG chain broken". You mention that the JTAG doesn't work if the exposed pad in the FPGA package is not connected to GND. I found this thread after searching a lot. Is there a document/manual that mentions this?

Altera_Forum
Honored Contributor II
452 Views

Thank you for u\your support. 

 

The board is working now and the problem where i stuck was due to the unaccounted grounding pad. 

 

drilled a hole and soldered it and the board worked... 

 

Thanks  

Saurabh
Altera_Forum
Honored Contributor II
452 Views

There have been several reports of people missing ground pads in their PCB designs. 

 

As a person who missed this information, can you please comment on why you think you missed reading this information in their data sheet. Perhaps Altera can improve the documentation by emphasizing the presence of the ground pad. Eg., when you built the footprint for the package, did it not have a ground pad in the recommended footprint documentation? 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor II
452 Views

Hey, 

 

There are two reasons i missed it and they are 

 

1. There is a file named PCG-01008 giving the detailed connection for using the device in jtag mode. But there is nothing that i can find about the grounding pad. 

 

2. And second reason is that when i made the Device library (using the BSDL file Provided by altera) and used it in schematic and board the grounding pad is not present both in schematic and the footprint. 

 

Regards, 

SAURABH
Altera_Forum
Honored Contributor II
452 Views

I am now facing problem burning the code in the EPCS4. 

 

I have made all the connection as give in the datasheet. 

 

Please let me know all the connections that are necessary and also driver required for the urJTAG software. 

 

Regards, 

SAURABH
Altera_Forum
Honored Contributor II
452 Views

I don't know about the urJTAG soytware, but you have basically 3 ways to program the flash: 

  1. directly connect your usb probe to the EPCS pins 

  2. configure the FPGA with a Sfl (Serial Flash Loader) image and access the EPCS through JTAG 

  3. configure the FPGA with a Nios CPU and an EPCS controller and use the Nios programmer 

Altera_Forum
Honored Contributor II
452 Views

Hello, 

 

I was wondering if we Quartus can detect my hardware for programming in JTAG mode.  

 

Currently I am using urJTAG software console to configure the hardware but there is some problem in communicating with the EPCS as it is not in JTAG chain. 

 

I tried to find a way of loading SFL on to the FPGA and the configuring the device but no success yet in that. 

 

 

There is a programmer provided in QUARTUS but it cant detect my board.  

 

what do I have to do to make the programmer detect my board... 

 

Thanks 

Saurabh
Altera_Forum
Honored Contributor II
452 Views

 

--- Quote Start ---  

 

There is a programmer provided in QUARTUS but it cant detect my board.  

 

what do I have to do to make the programmer detect my board... 

 

--- Quote End ---  

What are you using as your UrJTAG JTAG interface to communicate with the FPGA board? 

 

Unless your JTAG controller is a USB-Blaster, or other standard Altera device, it will not be detected by Quartus. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor II
452 Views

Hey DAVE, 

 

I am using a software called urJTAG. Its a command line base console. And we can send the send the svf file via this console to the FTDI which sends directly to the FPGA.  

 

When i use urjtag firstly i have to give a cable command which is "CABLE FT2232" 

 

the second command is "DETECT" which detect the device FPGA i am using. 

 

 

There should be some way the i can add my cable in quartus to make my board detected. 

 

THANKS,
Reply