Cyclone III programming problem (JTAG and AS)

[Altera_Forum]

Hello All, 

Please help! We have a problem with Cyclone III devices programming. We are using the board with 5 Cyclone III devices, connected in Combining JTAG and Serial (ESPC64) configuration. Figure 7-5 in Configuration Handbook and Figure 9-5 in Cyclone III device handbook. Bad things - it was errors in PCB layout, especially in configuration of MSEL pins on all FPGAs. And no way to fix it.  Now the question. Do we have chance to program FPGAs without AS configuration device?:confused:  Appresuated for any help.

[Altera_Forum]

--- Quote Start ---   When i use urjtag firstly i have to give a cable command which is "CABLE FT2232"  There should be some way the i can add my cable in quartus to make my board detected.   --- Quote End ---  Sorry, there is no support for this cable in Altera's software. They only support their own hardware.  Terasic sell USB-Blaster cables for $50.  http://www.terasic.com  You can also get cheap adapters that claim to be USB-Blaster compatible. The USB-Blaster is implemented using an FTDI FT245 and a CPLD. The CPLD implements something like the MPSSE mode that the FT2232 uses on your cable. The UrJTAG software knows the USB-Blaster protocol, so you can use that cable with UrJTAG. However, you cannot use any generic cable with the Altera Quartus software, as Altera have not made that interface public, so you cannot add new adapters that will be recognized by their software.  Cheers, Dave

[Altera_Forum]

Thanks DAVE for that information, 

 Actually my aim is to design a very low cost FPGA development board.  Now my FPGA board is working partially. By partially i mean the FPGA is getting configured but the EPCS is not getting loaded by the configuration data.  And I am trying to find out a way to load the config data in epcs.  What should I do to load the config data in the epcs using urJTAG. is it possible or not?  THANKS

[Altera_Forum]

--- Quote Start ---   What should I do to load the config data in the epcs using urJTAG. is it possible or not?   --- Quote End ---    Create an FPGA configuration that contains a JTAG-to-Avalon-MM master, or a component based on the SLD Virtual JTAG component, and then create an interface to the EPCS device.  Download the .sof image to the FPGA using UrJTAG.  Then communicate with the design and program the EPCS device.  Cycle the power, and your design will load from EPCS.  If you'd thought about your design a little more, you would have wired the FT2232 so that you could program the FPGA or the EPCS :)  Cheers, Dave

[Altera_Forum]

Hello Dave, 

 I have followed these step for ccreating the svf file given by altera.  Instantiating SFL Megafunction in the Quartus II Software Perform the following steps to generate an SFL megafunction instantiation. You must then instantiate the SFL megafunction in your FPGA top-level design. 1. On the Tools menu, click MegaWizard Plug-In Manager. Page 1 of MegaWizard Plug-In Manager appears. 2. Select the Create a new custom megafunction variation option and click Next. Page 2a of the MegaWizard Plug-In Manager appears, as shown in Figure 5. 3. Select the FPGA device family from the Which device family will you be using? pull-down list. 4. Select Serial Flash Loader from the JTAG-accessible Extensions category in the megafunction list. 5. Select the Hardware Description Language (HDL) output file type and name the file. Click Next (Verilog HDL was chosen for this example). 6. Specify the directory and output filename. Click Next. Page 3 of the MegaWizard Plug-In Manager appears, 7. Turn on the Share ASMI interface in the design check box if you must share the ASMI interface with your design. This option provides additional control pins for controlling the ASMI interface, as shown in Figure 7. 8. The Use enhanced mode SFL check box is turned on by default. This option provides more flexibility for JTAG cascading environment and the usage of the SFL with a third-party programmer tool. Turn off the Use enhanced mode SFL check box if you do not wish to use enhanced SFL. 9. Click Next until you reach the summary page. 10. Click Finish to generate the SFL megafunction. The Quartus II software generates the megafunction in the form of the HDL file you specified.   Converting .sof to .jic Files in the Quartus II Software To convert a .sof to a .jic file, perform the following steps: 1. On the File menu, select Convert Programming Files. 2. In the Convert Programming Files dialog box, select JTAG Indirect Configuration File (.jic) from the Programming file type drop down menu. 3. In the Configuration device field, specify the targeted serial configuration device. 4. In the File name field, browse to the target directory and specify an output file name. 5. Highlight the SOF Data in the Input files to convert window 6. Click Add File. 7. Select the .sof file that you want to convert to a .jic file. 8. Click OK. 9. Highlight FlashLoader and click Add Device 10. Click OK. The Select Devices dialog box appears. 11. Select the targeted FPGA that you are using to program the serial configuration device 12. Click OK. The Convert Programming Files dialog box appears 13. Click Generate.   To convert a .jic to a .jam file in the Quartus II software, perform the following steps: 1. On the Tools menu, select Programmer. 2. Click Add File. The Select Programming File dialog box appears. 3. Browse to the .jic file you created in “Converting .sof to .jic Files in the Quartus II Software” on page 10. Add more .jic files if you are programming multiple serial configuration devices. 4. Click Open. 5. Select Create/Update. In the File menu, scroll to Create JAM, SVF, or ISC File (refer to Figure 12). 6. The Create JAM, SVF, or ISC File dialog box appears 7. Click OK.   the only difference is that i have not create .jam file but .svf file.   but when i load the .svf file on to the board i get an error.   UrJTAG 0.10# 1502 Copyright (C) 2002, 2003 ETC s.r.o. Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors  UrJTAG is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for UrJTAG.  WARNING: UrJTAG may damage your hardware! Type "quit" to exit, "help" for help.  jtag> cable ft2232 Connected to libftd2xx driver. jtag> detect IR length: 10 Chain length: 1 Device Id: 00000010000011110001000011011101 (0x00000000020F10DD)  Manufacturer: Altera  Part(0): EP4CE10  Stepping: 1  Filename: d:\urjtag\data/altera/ep4ce10/ep4ce10 jtag> svf c:\test\fulladd.svf warning svf: unimplemented mode 'absent' for trst error svf: sir command length inconsistent.  in input file between line 34 col 1 and line 34 col 20 error occurred for svf command sir.     please let me know what and where i am doing it wrong.  THANKS Saurabh

[Altera_Forum]

--- Quote Start ---   please let me know what and where i am doing it wrong.   --- Quote End ---    From the error message, it looks like its an issue with UrJTAG.  Just buy a $50 Terasic USB-Blaster and be done with it.  If you're really interested in getting UrJTAG to work, then you'll have to modify UrJTAG to accept the Altera .SVF commands.  Cheers, Dave

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

bit 408 I ? IO49bit 409 C 1 *bit 410 O ? IO49 409 1 Zbit 411 O ? *bit 412 O 1 *bit 413 O ? *bit 414 O ? *bit 415 O 1 *bit 416 O ? *bit 417 O ? *bit 418 O 1 *bit 419 O ? *bit 420 O ? *bit 421 O 1 *bit 422 O ? *bit 423 O ? *bit 424 O 1 *bit 425 O ? *bit 426 O ? *bit 427 O 1 *bit 428 O ? *bit 429 O ? *bit 430 O 1 *bit 431 O ? *bit 432 O ? *bit 433 O 1 *bit 434 O ? *bit 435 O ? *bit 436 O 1 *bit 437 O ? *bit 438 I ? IO46bit 439 C 1 *bit 440 O ? IO46 439 1 Zbit 441 O ? *bit 442 O 1 *bit 443 O ? *bit 444 O ? *bit 445 O 1 *bit 446 O ? *bit 447 O ? *bit 448 O 1 *bit 449 O ? *bit 450 I ? IO44bit 451 C 1 *bit 452 O ? IO44 451 1 Zbit 453 I ? IO43bit 454 C 1 *bit 455 O ? IO43 454 1 Zbit 456 I ? IO42bit 457 C 1 *bit 458 O ? IO42 457 1 Zbit 459 O ? *bit 460 O 1 *bit 461 O ? *bit 462 O ? *bit 463 O 1 *bit 464 O ? *bit 465 O ? *bit 466 O 1 *bit 467 O ? *bit 468 O ? *bit 469 O 1 *bit 470 O ? *bit 471 O ? *bit 472 O 1 *bit 473 O ? *bit 474 I ? IO39bit 475 C 1 *bit 476 O ? IO39 475 1 Zbit 477 I ? IO38bit 478 C 1 *bit 479 O ? IO38 478 1 Zbit 480 O ? *bit 481 O 1 *bit 482 O ? *bit 483 O ? *bit 484 O 1 *bit 485 O ? *bit 486 O ? *bit 487 O 1 *bit 488 O ? *bit 489 I ? IO34bit 490 C 1 *bit 491 O ? IO34 490 1 Zbit 492 I ? IO33bit 493 C 1 *bit 494 O ? IO33 493 1 Zbit 495 I ? IO32bit 496 C 1 *bit 497 O ? IO32 496 1 Zbit 498 O ? *bit 499 O 1 *bit 500 O ? *bit 501 O ? *bit 502 O 1 * bit 503 O ? *bit 504 I ? IO31bit 505 C 1 *bit 506 O ? IO31 505 1 Zbit 507 O ? *bit 508 O 1 *bit 509 O ? *bit 510 I ? IO30bit 511 C 1 *bit 512 O ? IO30 511 1 Zbit 513 O ? *bit 514 O 1 *bit 515 O ? *bit 516 O ? *bit 517 O 1 *bit 518 O ? *bit 519 I ? IO28bit 520 C 1 *bit 521 O ? IO28 520 1 Zbit 522 O ? *bit 523 O 1 *bit 524 O ? *bit 525 O ? *bit 526 O 1 *bit 527 O ? *bit 528 O ? *bit 529 O 1 *bit 530 O ? *bit 531 O ? *bit 532 O 1 *bit 533 O ? *bit 534 I ? CLK3bit 535 O ? *bit 536 O ? *bit 537 I ? CLK2bit 538 O ? *bit 539 O ? *bit 540 I ? CLK1bit 541 O ? *bit 542 O ? *bit 543 O ? *bit 544 O 1 *bit 545 O ? *bit 546 O ? *bit 547 O 1 *bit 548 O ? *bit 549 O ? *bit 550 O 1 *bit 551 O ? *bit 552 I ? IO13bit 553 C 1 *bit 554 O ? IO13 553 1 Zbit 555 O ? *bit 556 O 1 *bit 557 O ? *bit 558 I ? IO11bit 559 C 1 *bit 560 O ? IO11 559 1 Zbit 561 I ? IO10bit 562 C 1 *bit 563 O ? IO10 562 1 Zbit 564 O ? *bit 565 O 1 *bit 566 O ? *bit 567 O ? *bit 568 O 1 *bit 569 O ? *bit 570 O ? *bit 571 O 1 *bit 572 O ? *bit 573 O ? *bit 574 O 1 *bit 575 O ? *bit 576 O ? *bit 577 O 1 *bit 578 O ? *bit 579 I ? IO8bit 580 C 1 *bit 581 O ? IO8 580 1 Zbit 582 I ? IO7bit 583 C 1 *bit 584 O ? IO7 583 1 Zbit 585 I ? IO6bit 586 C 1 *bit 587 O ? IO6 586 1 Zbit 588 O ? *bit 589 O 1 *bit 590 O ? *bit 591 O ? *bit 592 O 1 *bit 593 O ? *bit 594 I ? IO3bit 595 C 1 *bit 596 O ? IO3 595 1 Zbit 597 I ? IO2bit 598 C 1 *bit 599 O ? IO2 598 1 Zbit 600 I ? IO1bit 601 C 1 *bit 602 O ? IO1 601 1 Zthis is one of the urJTAG data file. can u tell me what is that modification i shall make... salias IO1 BSC200# Note: this pin is specified as I/O. If AS mode is specified by MSEL it is output only (ASDO)salias IO2 BSC199# Note: this pin is specified as I/O. If AS mode is specified by MSEL it is output only (nCSO)salias IO3 BSC198salias IO6 BSC195salias IO7 BSC194salias IO8 BSC193salias IO10 BSC187salias IO11 BSC186salias IO13 BSC184salias DATA0 BSC183# Family-specific input pin 14salias DCLK BSC182# Family-specific input pin 15salias CLK0 BSC181# Family-specific input pin 17salias CLK1 BSC180# Family-specific input pin 18salias CLK2 BSC179# Family-specific input pin 21salias CLK3 BSC178# Family-specific input pin 22salias IO28 BSC173salias IO30 BSC170salias IO31 BSC168salias IO32 BSC165salias IO33 BSC164salias IO34 BSC163salias IO38 BSC159salias IO39 BSC158salias IO42 BSC152salias IO43 BSC151salias IO44 BSC150salias IO46 BSC146salias IO49 BSC136salias IO50 BSC135salias IO51 BSC134salias IO52 BSC132salias IO53 BSC131salias IO54 BSC130salias IO55 BSC129salias IO58 BSC124salias IO59 BSC121salias IO60 BSC120salias IO64 BSC115salias IO65 BSC114salias IO66 BSC111salias IO67 BSC110salias IO68 BSC108salias IO69 BSC107salias IO70 BSC106salias IO71 BSC105salias IO72 BSC104salias IO73 BSC102salias IO74 BSC101salias MSEL1 BSC073# Family-specific input pin 84salias MSEL0 BSC074# Family-specific input pin 85salias IO75 BSC100salias IO76 BSC098salias CLK7 BSC079# Family-specific input pin 88salias CLK6 BSC078# Family-specific input pin 89salias CLK5 BSC077# Family-specific input pin 90salias CLK4 BSC076# Family-specific input pin 91salias IO77 BSC097salias IO80 BSC091salias IO83 BSC087salias IO84 BSC086salias IO85 BSC085salias IO86 BSC084salias IO87 BSC083salias IO98 BSC068salias IO99 BSC067salias IO100 BSC066salias IO101 BSC065salias IO103 BSC064salias IO104 BSC063salias IO105 BSC062salias IO106 BSC058salias IO110 BSC052salias IO111 BSC050salias IO112 BSC049salias IO113 BSC048salias IO114 BSC047salias IO115 BSC046salias IO119 BSC041salias IO120 BSC040salias IO121 BSC039salias IO124 BSC031salias IO125 BSC030salias IO126 BSC029salias IO127 BSC028salias IO128 BSC027salias IO129 BSC026salias IO132 BSC023salias IO133 BSC022salias IO135 BSC019salias IO136 BSC017salias IO137 BSC014salias IO138 BSC013salias IO141 BSC009salias IO142 BSC003salias IO143 BSC002salias IO144 BSC001 

   this is another data file for this device.i will be buying terasic usb blaster. but for that i need to make some changes in my board design. and that is going to take some time as the fabrication house will deliver the board after 10 to 20 days. till that time i would like to try to make this thing work.i feel there is a very small thing that i am missing and that can make it work....please just see to the above data file... and let me know if there is anything i can do to make this start working completely... :)THANKS A LOT DAVERegardsSaurabh

[Altera_Forum]

--- Quote Start ---   this is another data file for this device.   --- Quote End ---  And this is supposed to tell us what?    --- Quote Start ---   i will be buying terasic usb blaster. but for that i need to make some changes in my board design. and that is going to take some time as the fabrication house will deliver the board after 10 to 20 days.   --- Quote End ---  Why? If you have a board with TCK/TMS/TDI/TDO on a connector, you don't need to make a board change, just create an adapter cable if you have not used the standard 10-pin Altera header format.    --- Quote Start ---   till that time i would like to try to make this thing work.i feel there is a very small thing that i am missing and that can make it work....please just see to the above data file... and let me know if there is anything i can do to make this start working completely...  --- Quote End ---  Sorry, I'm not going to be able to help decrypt the .svf file format. Its just not that interesting. If I needed to decode the programming sequence, I would trace the JTAG transactions from an Altera USB-Blaster and then compare that to the .svf file, i.e., to reverse-engineer the programming sequence, start off with a working programmer.  Cheers, Dave

[Altera_Forum]

Hey DAVE, 

 I am still stuck with the same problem of getting my configuration data into the serial flash EPCS4.  I read about getting this task done and found that for getting the configuration data into the EPCS the serial flash loader concept has to made use. but on the other hand i also read that for that the fpga has to be in AS mode so the MSEL(2-0) has to be changed from (000) to (101). that is from JTAG mode to AS mode.  now if i set the mode to as then will the JTAG configuration scheme work.  regards saurabh

[Altera_Forum]

--- Quote Start ---   will the JTAG configuration scheme work.   --- Quote End ---    Read the user manual for the part. I believe JTAG should work for all the configuration schemes. If JTAG is not working, then that is the problem you have to solve first, not AS programming.  Cheers, Dave