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Cyclone IV GX LVDS placement and termination

Oliver_I_Sedlacek
New Contributor III
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I need to place 48 LVDS receiver pairs on to a 484 pin Cyclone IV GX package. I've been studying the Cyclone 4 handbook, specifically section 6 Table 6.2 and I'm still confused.

1. According to this the GX only supports true LVDS on banks 5 and 6, but that's not enough pins. Quartus is happy to allocate my LVDS inputs to other banks, but what is the downside?

2. I'd like to use OCT but table 6.2 just has a blank across the LVDS row. Does that mean LVDS OCT isn't supported?

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FvM
Valued Contributor III
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Hi,
1. "true LVDS" refers to transmitters, these banks support LVDS TX IO-standard, the other banks support only emulated LVDS with three resistor network. LVDS RX can be configured for all banks.

2. Cyclone III, IV and 10LP doesn't provide on-chip parallel termination (Rd) for LVDS RX. External 100 ohm resistors are required.

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FvM
Valued Contributor III
586 Views
Hi,
1. "true LVDS" refers to transmitters, these banks support LVDS TX IO-standard, the other banks support only emulated LVDS with three resistor network. LVDS RX can be configured for all banks.

2. Cyclone III, IV and 10LP doesn't provide on-chip parallel termination (Rd) for LVDS RX. External 100 ohm resistors are required.
Oliver_I_Sedlacek
New Contributor III
569 Views

Thanks, a really useful answer. I only need 6 LVDS transmitters so that shouldn't be a problem.

Re OCT you don't include the Cyclone IV GX in your list, is it different from the the Cyclone IV E?

Before I wrap this up, is there a diagram for the three resistor network for LVDS? Figures 6-7 and 6-8 only show HSTL and SSTL with four resistors.

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AqidAyman_Intel
Employee
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You can refer to the attached picture on below comment for the diagram of the emulated LVDS transmitters with three resistor networks.


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AqidAyman_Intel
Employee
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Figure 6–13. LVDS Interface with External Resistor Network on the Top and Bottom I/O Banks

AqidAyman_Intel
Employee
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