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Valued Contributor III
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Cyclone IV PLL min input frequency

Hi,  

 

What is minimum input clock for Cyclone IV E PLL? Data sheet states that minimum Fin=5MHz, but PLL locks even to 500KHz input clock freqency. Can someone explain this to me?  

 

Thanks
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Valued Contributor III
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As you've found, the spec states fIN(min)=5MHz. Don't rely on all devices operating correctly if you're operating them out of spec. 

 

The only suggestion I have is that the PLL is locking to some harmonic content of your clock source. 

 

Cheers, 

Alex
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Valued Contributor III
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I second Alex's recomendation. You will find that as temperature changes and/or electrical noise is added or even changes your PLL won't lock reliably any more. We had one in our lab that was sometimes locking to a WiFi router that was nearby rather than the way out of spec input signal. "It works in the lab, why doesn't it work at the customer's site"?

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Valued Contributor III
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Hi,  

 

Thanks for your answers. Then could someone help with the solution on how to implement interface when FPGA is clocked in range of 100kHz - 200MHz, and clock can be changed while operating? 

I have implemented reconfigurable PLL to cover range 5MHz to 200MHz, but currently i dont have any ideas on what to do when FPGA is clocked below 5 MHz.
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Valued Contributor III
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I suggest you'll have to use an independent, fixed clock to measure the frequency of your changeable clock. This will allow you to determine whether the clock is above of below a threshold - say 10MHz. I suggest you keep the threshold well away from 5MHz. You can then have two separate (potentially identical) blocks of logic; one clocked directly from your varying clock; the other from your reconfigurable PLL. Depending on the clock frequency, you either use the result from one portion of logic or the other. 

 

Cheers, 

Alex
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Valued Contributor III
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--- Quote Start ---  

I suggest you'll have to use an independent, fixed clock to measure the frequency of your changeable clock. This will allow you to determine whether the clock is above of below a threshold - say 10MHz. I suggest you keep the threshold well away from 5MHz. You can then have two separate (potentially identical) blocks of logic; one clocked directly from your varying clock; the other from your reconfigurable PLL. Depending on the clock frequency, you either use the result from one portion of logic or the other. 

 

Cheers, 

Alex 

--- Quote End ---  

 

 

Thanks for your suggestion. I am affraid that there is not enough FPGA memory resources to duplicate those blocks. I tried to bypass PLL output clock with dynamicaly controlled MUX, and providing direct clock to logic but no luck.  

 

Thanks again
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