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I want to configure a Cyclone IV part (EP4CE10F17C7) using passive serial mode from an onboard processor. The processor's I/O pins are all 1.8V logic level. I would think this would be fine if I set VDDIO for bank 1 (nCONFIG, DCLK and DATA0 pins) to 1.8V.
However, I have seen confusing information in the Cyclone IV handbook/datasheet/configuration handbook about the PS configuration requiring 2.5V IO. Does this mean 1.8V is not possible for this? Is it possible to configure using 1.8V Passive Serial, or do I have to set bank1 VDDIO to 2.5V and add a level converter?Link Copied
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Yes - you can configure Cyclone IV devices in PS mode at 1.8V.
A few gotchas to note. MSEL pins are tied to GND or VCCA, which needs to be powered at 2.5V. Also, CONF_DONE lives in bank 6. So it's pull-up resistor should be connected to the supply for bank 6, not bank 1. Cheers, Alex- Mark as New
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Alex, thank you very much. That's exactly what I was hoping to confirm. In my case, bank 6 is also 1.8V. And MSEL pins will all be grounded, so I think everything is good.
Given this, I'm confused by the documentation. Can anyone explain what the meaning of the "Configuration Voltage Standard" listed in the handbook Table 8-5 "Configuration Schemes for Cyclone IV E Devices" (see attached)? Under Passive Serial, MSEL=0000, it lists configuration voltages as 3.3, 3.0, 2.5. No 1.8V, am I missing something? https://www.alteraforum.com/forum/attachment.php?attachmentid=14842 As I had said, I plan to have MSEL=0000 and use 1.8V signals to configure. Despite the docs, I trust it will work.- Mark as New
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I hope I'm not missing something either. Indeed the entry does imply it doesn't support 1.8V I/O in PS mode.
I don't have anything definitive to offer. I'm hoping the documentation is lacking - although, given how mature the family is, I doubt it. Possibly a leftover from programming cable requirements when operating I/O bank 1 below 2.5V. USB-Blasters and other need at least 2.5V to power them... Cheers, Alex- Mark as New
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Following up now that I have boards built ...
- Good news ... I've had no problems configuring the FPGA with 1.8V I/O pins! - Summary of the setup:- Cyclone IV FPGA (EP4CE10F17C8)
- 3 MSEL pins pulled to GND (Passive Serial configuration)
- All banks powered by VCCIO=1.8V
- Using 1.8V LVCMOS signals directly attached to a processor to configure the FPGA.
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