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Cyclone V ALTLVDS_RX clocking

Honored Contributor II

Hello all, 


I am looking for some help trying to achieve a bank-usage-optimized pin assignment for a design.  


I need to receive data from 4 different LVDS interfaces in a Cyclone V GX C9 FPGA, where each interface need to use a dedicated corner FPLL, that is, using the 4 FPLLs available in the FPGA. 


According to the Cyclone V Device Handbook, there are restrictions regarding the use of fractional PLLs that drive LVDS receiver channels. Specifically, three of these restrictions are: 


  1. The corner fractional PLLs can drive the LVDS receiver and driver channels. However, the clock tree network cannot cross over to different I/O regions. For example, the top left corner fractional PLL cannot cross over to drive the LVDS receiver and driver channels on the top right I/O bank. 

  2. You must use the dedicated reference clock pin of the same I/O bank used by the data channel. 

  3. Each PLL can drive all the LVDS channels in the entire quadrant. 



However, from the documentation is not clear to which region are LVDS channels restricted for each corner FPLL. As an example, I could clock LVDS data channels in the banks# 3A,# 3B or# 4A, with an FPLL clocked by a clock input in the bank# 5A, which seems to contradict the second requirement I listed above.  


One option would be to use one I/O block for each interface, but this is not a nice solution since many pins of large I/O banks would be wasted, due to the VCC and VCCIO restrictions. 


Do you know if it is possible to know which LVDS SERDES pins can be clocked from a specific corner FPLL? 


Thanks for your help!!
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Honored Contributor II

Hi again, 


I just wanted to share my experience in case someone else needs it. 


For the last days I have been trying to understand which lvds channels can I drive with each corner fractional PLL and this is the conclusion I could get: 


- A corner fractional PLL can drive any of the LVDS channels of just one of its corner edges. 


As an example, the bottom-right corner FPLL can drive any LVDS channel of the FPGA bottom edge or the FPGA right edge but not LVDS channels of the FPGA bottom edge and right edge at the same time.  


For the different compilations I have carried out this rule seems to be right. I could not find any performance issue due to the usage of LVDS channels from different I/O banks within the same edge. 


In any case, I think this is some information Altera could provide in the FPGA documentation.