Does Altera provide a synchronization chain megafunction for asynchronous inputs

[Altera_Forum]

It is possible to write a synchronizer chain to synchronize incoming asynchronous signals and prevent metastability. It shall be a few lines of code. Does Altera have a special megafunction to do this or atleast some guidelines so Quartus understands that we are trying to infer a synchronization chain?

[Altera_Forum]

Volume 1 of the Quartus Prime handbook: Managing Metastability: 

 https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts-qpp-5v1.pdf  Since it's only a few lines of code to add registers, I don't think an IP is necessary.

[Altera_Forum]

--- Quote Start ---  It is possible to write a synchronizer chain to synchronize incoming asynchronous signals and prevent metastability. It shall be a few lines of code. Does Altera have a special megafunction to do this or atleast some guidelines so Quartus understands that we are trying to infer a synchronization chain?  --- Quote End ---    Make your own, it is not hard. Define a verilog module that has CLK, IN, and OUT ports, and internally does an N-rank pipeline delay synchronizer between IN and OUT based on CLK. Then you can instantiate this module however many times you want.  For extra credit you can add a parameter input that specifies the number of levels of delay you want (defaulting to two, for example) but allows you do parameterize the module, if needed.  And you could make the IN and OUT be programmable width, instead of just a default of one bit wide.

[Altera_Forum]

If the incoming signals are a bus of common signals, your best using dcfifo