Cyclone V Altera PLL Can't do 100 MHz.

[Altera_Forum]

Hello, I am desiging a custom board based on the Altera Cyclone V board. I've changed the board oscillator from 50 MHz to 100 MHz. I am trying to make it go throught a PLL inside QSys and then feed 100 MHz to the rest of the design. 

 However I am having problems, I made a SDC and I am having timining problems, says my fmax of the ALT PLL output is 91.73 MHz.  I used to use altpll and everything used to work, but altppl is not compatible to Cyclone V so I have to use the Altera PLL.  What can I do? I've played a little bit with Quartus II configurations and the sdc file but it was useless...

[Altera_Forum]

Dear aprado, 

 Which version of Quartus tool is being used?  Because: in Quartus 13.x all timing constraints are preliminary. From latest Quartus 14.0 this functionality has been finalized.  I have also a question: How you can re-assign FPGA pins at the your PCB design procedure without the usage of FPGA Pin planner. Unfortunately, I observed, that in all latest versions of Quartus (13.0 - 14.0) the Pin planner (Live checker) does not function properly :  " Live I/O check is currently not supported by the "<name>" family. (ID: 168014) http://quartushelp.altera.com/14.0/master.htm#mergedprojects/msgs/msgs/efiochk_live_io_check_not_supported_for_family.htm "  Regards,  Zsolt

[Altera_Forum]

I am using Quartus II 14.0 and I 

don't know how to answer your question :(

[Altera_Forum]

Can it be that your misunderstanding the timing report? I guess the problem is that your design can't run at 100 MHz, the PLL shouldn't have problems to generate 100 Mhz (or 200 MHz).

[Altera_Forum]

--- Quote Start ---  Can it be that your misunderstanding the timing report? I guess the problem is that your design can't run at 100 MHz, the PLL shouldn't have problems to generate 100 Mhz (or 200 MHz).  --- Quote End ---    It could be but when I take out the DMA of the Bridge I have no timing problems, All I have in this bridge (FPGA2SDRAM) is a TSE MAC and a DMA and that's pretty much my whole design... If the timing report says this FMAX is 91.73 MHz I don't have much to misunderstand, do I?  Thanks

[Altera_Forum]

It's not a PLL problem. You can get detail report about failing pathes in TimeQuest to narrow down the issue.

[Altera_Forum]

--- Quote Start ---  It's not a PLL problem. You can get detail report about failing pathes in TimeQuest to narrow down the issue.  --- Quote End ---    I know it's not a PLL per se problem, I think I really made the wrong question. I would like to know the the FPGA2SDRAM / FPGA2HPS LW bridges can run at 100MHz;  I get the top falling path from the SOC System LW Bridge to the HPS System with a slack of -0.4

[Altera_Forum]

If fmax is only 91.73 MHz instead of 100 MHz the following things should be investigated: 

 - .sdc proper timing constraints must be added to this clock pin. - if PLL has a problem, it is always displayed be the Qsys GUI if configuring the Altera PLL IP ( clock not compensated .... e.g 100 MHz vs. 99.9 MHz)  I think your problem is the first, bad or missing timing constraints. I suggest to look the following good documentation: http://www.alterawiki.com/wiki/timequest_user_guide

[Altera_Forum]

--- Quote Start ---  It could be but when I take out the DMA of the Bridge I have no timing problems, All I have in this bridge (FPGA2SDRAM) is a TSE MAC and a DMA and that's pretty much my whole design... If the timing report says this FMAX is 91.73 MHz I don't have much to misunderstand, do I?  Thanks  --- Quote End ---    I think you have timing constraint problem. - check .sdc file for the clock signal and add a proper timing constraint  It is not a Altera PLL IP problem (you can check it in Qsys GUI, that all clocks compensated. It it has a problem that means 99.9 Mhz instead of 100 MHz).  I suggest to examine the following good documentation. http://www.alterawiki.com/wiki/timequest_user_guide

[Altera_Forum]

--- Quote Start ---  I know it's not a PLL per se problem, I think I really made the wrong question. I would like to know the the FPGA2SDRAM / FPGA2HPS LW bridges can run at 100MHz;  I get the top falling path from the SOC System LW Bridge to the HPS System with a slack of -0.4  --- Quote End ---    I have tested all bridges (H2F, F2H, H2F_LW). They can work ~ 100 / 133 / 166 MHz clock frequencies. I have no information about the FPGA2SDRAM interfaces. (note. this is a interface, not a bridge).

[Altera_Forum]

--- Quote Start ---  I have tested all bridges (H2F, F2H, H2F_LW). They can work ~ 100 / 133 / 166 MHz clock frequencies. I have no information about the FPGA2SDRAM interfaces. (note. this is a interface, not a bridge).  --- Quote End ---    Thanks for your answer, which FPGA have you used? Did you connect more than one component to the F2H/H2F/H2F_LW bridge? I have the problem when I connect a DMA and the TSE Mac to the F2S bridge.

[Altera_Forum]

--- Quote Start ---  Thanks for your answer, which FPGA have you used? Did you connect more than one component to the F2H/H2F/H2F_LW bridge? I have the problem when I connect a DMA and the TSE Mac to the F2S bridge.  --- Quote End ---    Dear Aprado,  For example: Several Altera DMAs inserted and tried on FPGA side, which utilized F2H bridge. The FPGA-SDRAM interfaces has not been used, yet. Target platform was Cyclone V SoC DB rev.D (5CSXFC6D6F31C6). TSE MAC : Why are not you use the HPS' EMAC instead of FPGA TSE_MAC?  Zs.V

[Altera_Forum]

--- Quote Start ---    I have also a question: How you can re-assign FPGA pins at the your PCB design procedure without the usage of FPGA Pin planner. Unfortunately, I observed, that in all latest versions of Quartus (13.0 - 14.0) the Pin planner (Live checker) does not function properly :  " Live I/O check is currently not supported by the "<name>" family. (ID: 168014) http://quartushelp.altera.com/14.0/master.htm#mergedprojects/msgs/msgs/efiochk_live_io_check_not_supported_for_family.htm "  Regards,  Zsolt  --- Quote End ---    Answer for my question: The "Early IO Assignment Analysis" or "IO Analysis before a compilation" might be an alternative solution instead of Live I/O checker.  The "I/O Assignment analysis" (Pin Planner) was successfully tested for Cyclone V SoC.   Moreover, Live IO check will not be supported in the current (14.0) and future release for Cyclone V.  Zs.V.

[Altera_Forum]

Thank you very much for your answer, unfortunately I have some custom IP which interfaces directly with the TSE MAC. 

 Cheers   --- Quote Start ---  Dear Aprado,  For example: Several Altera DMAs inserted and tried on FPGA side, which utilized F2H bridge. The FPGA-SDRAM interfaces has not been used, yet. Target platform was Cyclone V SoC DB rev.D (5CSXFC6D6F31C6). TSE MAC : Why are not you use the HPS' EMAC instead of FPGA TSE_MAC?  Zs.V  --- Quote End ---