Cyclone V E and DDR3 connection

[Altera_Forum]

Hi 

  I did a FPGA Board on myself and I don't get the DDR3 working correctly. While reading the "External Memory Interface Handbook Volume 3: Reference Material" and the calibration I got the following thought: Was it a bad idea to mix up the DQ signals? To have a simpler routing I changed some singalt in each DQS-region, like: 0,1,2,3,4,5,6,7 --> 5,2,6,1,0,3,4,7    Could this be a problem for the calibration since it startes with toggling just some DQs?   I get the "Write Calibration - Per-bit write deskew failure" when I do the calibration with the EMIF Tool    Your help is greatly appreciated

[Altera_Forum]

Hi again 

 I just found out with playing around with the soft memory controller, that it is ok to exchange the data lines. But my mistake was to exchange also the bank lines.   Could somebody verify my observation?  - It is allowed to exchange the data lines on PCB in each DQS-region, like: 0,1,2,3,4,5,6,7 --> 5,2,6,1,0,3,4,7. The HMC DDR3 interface which doen't  know anything about the mixing writes for example Bit 0 to bit 5, but with reading Bit 0 at 5 it gets corrected automatically.  - It is not allowed to exchange some address or bank lines  Your help is greatly appreciated

[Altera_Forum]

I think solution id: rd06102013_643 (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd06102013_643.html) covers this. Bit swapping within a byte lane is fine. However, if you want to move DQS pins you need to move all the DQ pins within that group with it. 

 Cheers, Alex