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Cyclone V GX using all 6 transceivers in both directions

Altera_Forum
Honored Contributor II
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I want to use all 6 transceivers for Gb Ethernet communication but I'm having trouble with the IP and assigning a TX PLL that is not from one of the channels as these are all used for RX. 

 

Is it at all possible to use all 6 transceivers at once, and how do I then solve the TX PLL issue? 

 

I have connected a 125MHz LVDS clock to one of the Refclk inputs of the transceiver blocks.
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Altera_Forum
Honored Contributor II
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Hi, 

 

You would need to leave one unused RX channel for the CMU PLL purpose. Probably you could try to explore using fPLL to clock your channels.
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Altera_Forum
Honored Contributor II
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Or you can look for larger device with additional transceiver channels ie 9 channels device.

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Altera_Forum
Honored Contributor II
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That is also what I have arrived at at this point, but what sense is there in advertising that you have 6 transceivers (a transceiver is a combined TX/RX device) when you can always only use 5 of them at a time? 

 

Is there really no other way to clock the transmitters than using of the channel CMU PLL's? 

 

The documentation is very hard to figure out and understand, and I'm having a hard time getting an clear overview of how things are connected and what's possible or not. 

 

The solution of using an even larger fpga would generate a huge price penalty which is not acceptable. We have chosen and designed around an fpga having 6 transceivers which is what we need, but I wouldn't in a million years have guessed that I could only to use 5 of them.
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Altera_Forum
Honored Contributor II
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As I read the literature, I should be able to source a fPLL from one of the RefClk inputs in the transceiver banks, and then use this fPLL to source all transmitters. All channel CMU PLLs are to be used as CDR PLLs. 

 

***************************************************************************************** 

Transmitter PLL 

In Cyclone V GX/GT/SX/ST devices, there are two transmitter PLL sources: CMU PLL (channel PLL) and 

fPLL. The channel PLL can be used as CMU PLL to clock the transceivers or as clock data recovery (CDR) 

PLL. 

***************************************************************************************** 

 

Is this possible?
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Altera_Forum
Honored Contributor II
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It is possible to use fPLL to clock all the 6 transmitters. You can try to test out a test design and run through Fitter compilation.

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Altera_Forum
Honored Contributor II
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That's the answer we were looking for. Now we only need to make it work. No luck so far, but knowing that it at least can be done helps.

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Altera_Forum
Honored Contributor II
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What is the issue or Quartus error that you encounter?

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Altera_Forum
Honored Contributor II
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Our guy who is in charge of synthesizing the project, is right now working on a version with only 5 transceivers running so that software development has something to work with. But the main problem was that Quartus would not accept not using one of the transceiver channel CMU PLLs for the transmitters. I will have to get back to you when we get time to work on this issue again.

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Altera_Forum
Honored Contributor II
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let me know when you have more details on the error.

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Altera_Forum
Honored Contributor II
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Thank you, I'll do that but it may not be right away.

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Altera_Forum
Honored Contributor II
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No problem.

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Altera_Forum
Honored Contributor II
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Has anyone figured out if it is possible to use all the transceivers? I have the same problem using all 6 transceivers. The documentation says that an external PLL can be used for the transmit PLL, so I did that. What they don't tell you anywhere that I could find is that in order for the external PLL to get to the transceivers, they route it through a clock divider. The clock divider is part of a transceiver, so it keeps me from using the transceiver where the clock divider is. A quick look at the Chip Planner shows this. 

 

What makes things worse is that I need to have all the transceivers work at two different rates that are not switchable by the transmit divider. So feeding 2 clocks from external PLLs eliminates using 2 transceivers, leaving only four usable.
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Altera_Forum
Honored Contributor II
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I'm currently investigating the clock options for Cyclone V as well and what I learnt so far is that you CAN use all 6 channels, but you must use the fPPLs for TX located in the 'PLL strip' (not the ones in the corners). They take one of the refclks as input. Caveat: only up to 3.125 Gbps !

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Altera_Forum
Honored Contributor II
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Hi! 

Can you post a sample project with reconfigurable duplex transceivers (that contain more than one data channel)? 

I cant build any configuration described in docs (with 2 or more data rates with 2 or more data channels) and so confused with it. Thanks!
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Click_Er
Beginner
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I'm working on something similar.

 

Cyclone V GX Transceiver setup

 

I'm putting together a 2 channel transceiver design on a cyclone V GX device. This device has 3 channels. I want to use channel 1 and 3 since the custom board has already been designed and wired to these channels. All 3 channels are on the same bank in this device. Can I use IP wizard and generate a channel with its PLL. After that is done, can I simply instantiate the generated IP second time and wire it up to the dedicated pins? Will my approach work? Or do I need to create a 2 channel IP?

 

Thanks.

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