Hello,I am implementing the SATA protocol on a Cyclone V FPGA. So far I have everything working with an older (SATA GEN 1) device, but to move to a newer device, I need a way to determine if the incoming data matches the speed I am expecting. In particular, after the OOB signals have been sent for the Physical Layer handshake, a device will send out data starting at 6.0 Gbps (if supported), then after some time 3.0 Gbps (if supported), and finally at 1.5 Gbps. In order to handle this change in speed, I have configured the Native Phy Transceiver with the set_locktodata and set_locktoref inputs enabled. The issue is that I have no way of knowing when the device begins to send data at the speed for which my transceivers are configured (1.5 Gbps), so that I should trigger set_locktodata to go high and set_locktoref to go low. The Cyclone V Transceiver Handbook states: "In manual lock mode, your design must include a mechanism—similar to a PPM detector—that ensures the CDR PLL output clock is kept close to the optimum recovered clock rate before recovering the clock and data" My question is, how can I know when the CDR output clock matches the optimum recovered clock rate? Is the best way to accomplish this task to build a PPM detector between a known clock and rx_clkout, assert set_locktodata, and then simply wait until the PPM detector reads valid levels? It seems that in the past, Altera provided the CDR output clock to the user by means of rx_clklow (see: https://www.altera.com/zh_cn/pdfs/literature/ug/xcvr_user_guide.pdf), but this signal is no longer available. Is there any way I can access the CDR PLL output clock, but leave the transceivers in locktoref mode? It seems that there should be some way to detect if the CDR is successfully recovering the clock from the data stream without asserting rx_setlocktodata when I know that the incoming data does not match the settings of the CDR. Thanks in advance for the insight! -NWL
As a quick follow up to this, I noticed that one can also export rx_pma_clkout from the Native Transceiver. According to the user guide, rx_pma_clkout: is" the RX parallel clockwhich is recovered from the serial received data is anoutput of the PMA", and seems like it maybe is the clock that should be monitored to check if the CDR is locked to data at the right speed?When checking this with signal tap, however, I didn't see this change with variable data speed, it just looked like rx_clkout multiplied by the serialization factor. Any tips?