Hi,
I'm currently working on a Cyclone V SX and i've got a little problem regarding LVDS clocking.
I've got a 33 MHZ clock feeding my FPGA from the bottom bank 3A and I want to drive LVDS channels in the Top Bank (8A).
When I use a PLL to generate a 50 MHz to feed an External LVDS PLL, i've got an error message :
Error (12499): Input clock of PLL (...), which drives at least one non-DPA mode SERDES, must be driven by a dedicated clock pin of the PLL.
This is indeed describes in the Cyclone V Clocking Handbook.
Then I tried to feed directly my LVDS PLL with my 33 Mhz clock but the PLL is instantiated in bottom left Factionnal PLL and can't drive LVDS pin in the Top Bank.
I must have missed an option for cascading PLL but i don't see a solution for my problem at the moment.
If someone can give me some light on this problem, i'll be greatly thankful
Thank you
