Cyclone V SoC - Shared Memory Controller

[Altera_Forum]

Hi @all, 

 I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller.  I set up a QSYS-System with the connections and now try to get data from this Memory.  I have seen something like that there must be set some registers in the HPS to open the connection, (like with the HPS<->FPGA bridges), but I don't get the preloader generated by my design run correctly. And if I set the registervalues in HPS by hand, nothing happend on this interface.  Has anyone set up a system with the shared memorycontroller working and could give me a hint to the right direction?

[Altera_Forum]

waitrequest is an output of the memory controller, so i'm not sure the F2H port would be the problem. can you check the status signals of the memory controller to see if it has passed calibration?

[Altera_Forum]

Thanks for the reply thepancake, I have just discovered that the reason waitrequest was high. The preloader file needs to be updated following the change to the HPS component to add the FPGA to HPS SDRAM port to the HPS SDRAM controller configuration. My problem was that the preloader did not correctly re-generate (see below). 

 Apparently you need to delete the entire spl-bsp directory before generating the pre-loader. When I attempted to make the preloader generating in bsp-editor, then running the makefile in the spl-bsp directory, the generated preloader file (preloader-mkpimage.bin) did not change. Once I deleted the entire spl-bsp folder and re-generated, this time the preloader file was changed. Once I ran using this pre-loader, the SDRAM to FPGA avalon interface appears to work normally (i.e. waitrequest is low until the controller is busy).  However, the problem I am now having is that when I attempt a read from the FPGA I cause the system to crash (terminal freezes and HPS requires a hard reset) and no data is returned to the FPGA (Read Valid is never set) Possibly I am attempting to access an area of RAM that I shouldn't be?  I am not certain of how the HPS SDRAM maps to the avalon interface but the area I am trying to access is the area that I think is being assigned by the rocketboards example module http://www.rocketboards.org/foswiki/.../myfirstmodule

[Altera_Forum]

That sounds like the bridge hasn't been opened up. For a master in the HPS (like the CPU) to be able to access anything in the FPGA the following is required: 

 1 - Bridge needs to be clocked and pulled out of reset 2 - Bridge needs to be enabled in the address map (this is enabled in the GPV of the L3 interconnect)  By default the HPS-to-FPGA bridges are not mapped in after the system comes out of reset so software has to do that.

[Altera_Forum]

oops, that makes sense i didn't realize you were using the HPS memory controller

[Altera_Forum]

Taz1984, 

 Were you able to resolve your issue with DS-5? I have been trying to access the hps sdram from the fpga side using the f2h_sdram interfaces with no success. I'm not sure why, but if I try to access SDRAM from the FPGA side, the DS-5 debugger looses communications with the MPU. This indicates to me that accessing the SDRAM from the FPGA side is locking up the SDRAM controller and crashing the MPU. I'm trying to understand what has to be done in the SDRAM controller to properly configure the f2h_sdram interfaces, and whether this should happen in the preloader or the u-boot process?  I appreciate any insight anyone may have on this issue.  Thanks -kstolp

[Altera_Forum]

Hi kstolp, 

 I have got a working block in the FPGA that masters transfers from HPS RAM to FPGA RAM. I experienced a similar issue along the way (many times!), the HPS seems to 'hang' so the terminal freezes up and if you are debugging you lose the connection. This happens from my experience for one of two reasons, the HPS is attempting to address a slave bus that is not yet configured (e.g. if the fpga has not been programmed or there is a problem with your FPGA design).  The second reason is if you attempt to access an area of HPS RAM that you're not supposed to (I'm guessing the OS is doing something critical with the data stored in these locations?). I don't know why but accesses to some areas caused my design to crash.  I used the example module http://www.rocketboards.org/foswiki/.../myfirstmodule. This allocates a buffer in HPS RAM and, importantly, you can read the physical address of the buffer. This allows the FPGA to access data that your application copies into this buffer. This is safer since you know that this area in the HPS RAM will only have your data in. In my design I had to divide the physical address by 4 (to make 32-bit aligned) and add an offset of 0x2000 0000 (I don't know why!) to get the physical address of my HPS buffer from the FPGA viewpoint. I found this out mainly by trial and error.  It should be possible to do allocate the buffer using kmalloc() in your code and then get the physical address using virt_to_phys() but I have not been able to get this working due to issues with the compiler, but this is done for you if you use the module anyway.

[Altera_Forum]

Also I forgot to add that you need to make sure you re-generate the preloader when you change your HPS to have the F2H SDRAM port in QSYS. I had to delete the entire spl-bsp directory before generating the pre-loader since there is a bug which means it doesn't update some files if they already exist. 

 If the preloader doesn't know about the F2H SDRAM port it will not be correctly configured and when you attempt to read it crashes (I also experienced this).

[Altera_Forum]

Dave, 

 Thanks for the feedback. I will try your lessons learned in my design. The 0x2000_0000 offset you add is interesting. It would be nice to know why, but for now, I'll give it a try. I assume you are using the address span extender to interface your fpga masters to the F2H SDRAM port (as BadOmen has pointed out). Is this correct?  I was already doing your preloader delete the directory trick. One thing that has not been obvious to me is where the F2H SDRAM port is configured in the software chain. You have indicated that this does get taken care of by the preloader generated by the bsp-editor. Other than the preloader trick, is there anything else that needs to be done to configure the F2H SDRAM port? BadOmen has stated that the bridges need to be taken out of reset. I have not come across such a requirement for the F2H SDRAM port. Is this your understanding as well?  Thanks again, -kstolp

[Altera_Forum]

Hi kstolp, 

 I did not use the address expander. I prefer to access the Avalon-MM bus directly since I am not connecting to a NIOS on the FPGA but only to my own FPGA logic which can address the memory with no issues. I've found the avalon interface to be pretty user friendly so it didn't take long to write some VHDL to access the port.  I have not had to explicitly take any of the bridges out of reset, although I believe the way to do this is to write directly to the "rstmgr > brgmodrst" registers at 0xFFD0501C (see http://www.altera.com/literature/hb/cyclone-v/hps.html)  I know that the pre-loader does something differently after you enable the F2H SDRAM port since it changes some of the generated software files are changed (e.g. hps.xml <config name='F2SDRAM_READ_PORT_USED' value='1' />). If you don't update the pre-loader then the avalon-MM interface to your F2H SDRAM port will hold "waitrequest" high and so you can't request any reads or writes (maybe because the bridge was in reset?).  I think that the pre-loader must be taking the bridges out of reset since I am not doing this in my application code?

[Altera_Forum]

I've been searching for any pointers to enable read / write access of HPS ram from the FPGA but cannot find any example code. 

The rocket board link fails (even when I have logged into the rocket board site), could you confirm the link or (big ask) share your project?      --- Quote Start ---  Hi kstolp,  I have got a working block in the FPGA that masters transfers from HPS RAM to FPGA RAM. I experienced a similar issue along the way (many times!), the HPS seems to 'hang' so the terminal freezes up and if you are debugging you lose the connection. This happens from my experience for one of two reasons, the HPS is attempting to address a slave bus that is not yet configured (e.g. if the fpga has not been programmed or there is a problem with your FPGA design).  The second reason is if you attempt to access an area of HPS RAM that you're not supposed to (I'm guessing the OS is doing something critical with the data stored in these locations?). I don't know why but accesses to some areas caused my design to crash.  I used the example module http://www.rocketboards.org/foswiki/.../myfirstmodule. This allocates a buffer in HPS RAM and, importantly, you can read the physical address of the buffer. This allows the FPGA to access data that your application copies into this buffer. This is safer since you know that this area in the HPS RAM will only have your data in. In my design I had to divide the physical address by 4 (to make 32-bit aligned) and add an offset of 0x2000 0000 (I don't know why!) to get the physical address of my HPS buffer from the FPGA viewpoint. I found this out mainly by trial and error.  It should be possible to do allocate the buffer using kmalloc() in your code and then get the physical address using virt_to_phys() but I have not been able to get this working due to issues with the compiler, but this is done for you if you use the module anyway.  --- Quote End ---  

[Altera_Forum]

--- Quote Start ---  I've been searching for any pointers to enable read / write access of HPS ram from the FPGA but cannot find any example code. The rocket board link fails (even when I have logged into the rocket board site), could you confirm the link or (big ask) share your project?  --- Quote End ---    Link: http://www.rocketboards.org/foswiki/projects/myfirstmodule

[Altera_Forum]

Hi all 

I had a test just now, succeed in transfering test data form FPGA to SDRAM controller.  But it only works in bare metal now, i don't kown if it helps The steps : 1 , Launch Qsys, Add a FPGA-to-SDRAM interface in hps, select the avalon MM write-only mode 2. Edit a Write-burst Soft IP base on Avalon MM master interface, add it to Qsys and connect it to the f2h sdram data interface in setp1 3. After compiling, debug preloader in DS-5 , I see the test in the memory window.

[Altera_Forum]

Dear voroshazi! 

I am student, I have just studied SocKit Cyclone V, my goal is to access FPGA SDRAM from HPS through HPS2FPGA AXI Bridge, I still don't know how to implement this project. Do you give me a device and related document. I am looking forward your response. Thank you so much!

[Altera_Forum]

--- Quote Start ---  Dear BadOmen,  Here is a feedback for your comments as I promised.  According to your previous post I have also managed to access now the FPGA SDRAM / internal BRAM from the HPS portion (ARM side) at HWLib level. The key was to release the bridges from reset (init_bridge in hwlib.c). However, without DMA I have measured only 10 - 15 MB/s memory throughput (between ARM vs. FPGA memory) across HPS2FPGA bridge. Do you suggest any reference design, which integrates (FW/SW) and uses DMA?  What is the role the h2f_reset signal in HPS (cylcone V handbook gives a few info)? Because as I experienced if I left this signal unconnected in qsys I can use both FPGA memory and HPS memory in a same FW design? The debounce circuit is also eliminated from golden HW/SW reference design.  "Address Span Expander" bridge will be a good IP in the future, but I set all memory address spaces to a narrower size in order to be accessed by a 32-bit addresses of Nios II processor.  Regards,  ZS.V.  --- Quote End ---   Dear voroshazi! I am student, I have just studied SocKit Cyclone V, my goal is to access FPGA SDRAM from HPS through HPS2FPGA AXI Bridge, I still don't know how to implement this project. Do you give me a device and related document. I am looking forward your response. Thank you so much!

[Altera_Forum]

Also when using the FPGA-to-SDRAM ports after configuring the hardware I recommend writing to the applycfg bit as well which ensures the SDRAM port settings get set properly in the SDRAM controller. You can find this bit in the staticcfg register. You have to make sure the SDRAM controller is idle when writing to this bit so make sure you are executing code in another memory (on-chip RAM for example) when you write to the register.

[Altera_Forum]

--- Quote Start ---  Link: http://www.rocketboards.org/foswiki/projects/myfirstmodule  --- Quote End ---    This is SW. However, is there any HW/SW combined example for FPGA-to-SDRAM interfaces?

[Altera_Forum]

--- Quote Start ---  This is SW. However, is there any HW/SW combined example for FPGA-to-SDRAM interfaces?  --- Quote End ---    I have the same question.

[Altera_Forum]

I've got a working HW/SW example project illustrating FPGA-HPS SDRAM interface verifiable from the FPGA side via System Console and from the ARM Linux side via devmem tool. PM me if you would like the Quartus Project and source code!

[Altera_Forum]

Hi -- I would really appreciate a copy of the example project. Apparently I don't have enough posts here to be able to PM you directly, but if you wouldn't mind sharing I would appreciate it.  

Thanks Lance (lance @ RFdude.com )

[Altera_Forum]

--- Quote Start ---  I've got a working HW/SW example project illustrating FPGA-HPS SDRAM interface verifiable from the FPGA side via System Console and from the ARM Linux side via devmem tool. PM me if you would like the Quartus Project and source code!  --- Quote End ---   Could you send me a copy of the project and the source code? My email is garyliu2016@sina.com. Thank you!

[Altera_Forum]

--- Quote Start ---  I've got a working HW/SW example project illustrating FPGA-HPS SDRAM interface verifiable from the FPGA side via System Console and from the ARM Linux side via devmem tool. PM me if you would like the Quartus Project and source code!  --- Quote End ---    Hi,  I would really appreciate a copy of your project if you don't mind sharing to get more experience with the FPGA-HPS bridges.  nalkhateeb@teamist.com