Cyclone V SoC - Shared Memory Controller

[Altera_Forum]

Hi @all, 

 I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller.  I set up a QSYS-System with the connections and now try to get data from this Memory.  I have seen something like that there must be set some registers in the HPS to open the connection, (like with the HPS<->FPGA bridges), but I don't get the preloader generated by my design run correctly. And if I set the registervalues in HPS by hand, nothing happend on this interface.  Has anyone set up a system with the shared memorycontroller working and could give me a hint to the right direction?

[Altera_Forum]

Can either of you guys point me to a good example of this approach? Thanks -

[Altera_Forum]

--- Quote Start ---  I've got a working HW/SW example project illustrating FPGA-HPS SDRAM interface verifiable from the FPGA side via System Console and from the ARM Linux side via devmem tool. PM me if you would like the Quartus Project and source code!  --- Quote End ---    This is exactly what I'm trying to do, but I have not been able to get it working. It would be great to see a good example - I'm unable to PM you so can you send it to me at cmjcampbell@gmail.com? Thank you!

[Altera_Forum]

I am also interested in looking through an example project. I've been struggling with the FPGA-to-HPS SDRAM interface for a few weeks and haven't gotten anywhere. 

 WH2011, would you be able to post your example project publicly?

[Altera_Forum]

Hi , could you share your example please. My mail is mecatronicman@hotmail.com 

Thanks

[Altera_Forum]

--- Quote Start ---  I've got a working HW/SW example project illustrating FPGA-HPS SDRAM interface verifiable from the FPGA side via System Console and from the ARM Linux side via devmem tool. PM me if you would like the Quartus Project and source code!  --- Quote End ---    Hi,  If you still have it, I would really appreciate a copy of the project and the source code. My email is dylanchippy@gmail.com  Thanks a lot

[Altera_Forum]

--- Quote Start ---  I've got a working HW/SW example project illustrating FPGA-HPS SDRAM interface verifiable from the FPGA side via System Console and from the ARM Linux side via devmem tool. PM me if you would like the Quartus Project and source code!  --- Quote End ---    Hi WH2011,  I would greatly appreciate a copy of your project. Could you email it to "felixw256 _at_ gmail _dot_ com"?  Many thanks, Felix

[Altera_Forum]

I'm trying to get the FPGA to HPS SDRAM interface working but it just freezes on memory access. I have set up a Avalon-MM Read/Write port on a DE0-nano-SoC. I have tried reading or writing to a lot of different addresses but the result remains the same.  

 * What address are you using? I have done most of the testing with 0x30000000 which should hit the ram regardless of the 0x20000000 offset described in this thread. * Have you seen any examples of this that is compatible with DE0-nano SoC? * Is it enough to build the preloader? I built the preloader from my fpga project but then I imported another U-boot because my preloader would not work with U-boot from the SD image. I also had to replace the kernel, so a lot of the hardware fails to initialize. So far I believe that this should be ok for testing as long as the SDRAM controller gets initialized by the preloader. I can see that the reset bits for the FPGA to SDRAM ports gets set when I use this setup. * Is there any way to catch this error in a more controlled way than freezing? * In case I need to create a bare minimum fpga project to test this, what example should I use as a base?  I have a deep understanding of the FPGA part but my linux skills are still at a very basic level.

[Altera_Forum]

For accessing the HPS SDRAM via the F2S bridge, please note that you need to follow the steps as described here: 

https://www.altera.com/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html?utm_source=altera&utm_medium=newsletter&utm_campaign=facts&utm_content=na_how_can_i_enable_ki_15_08_2016

[Altera_Forum]

This design was recently ported to the Cyclone V development kit which you might find useful: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html

[Altera_Forum]

good example! mark