First of all, I am a novice when it comes to soc development. I was trying to implement Intel's FPGA-to-HPS Bridges Design Example (https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/soc/f...) on my DE1-SoC board.
I edited the quartus files to reflect the SDRAM timings of this board, ran tcl scripts and updated the main verilog file to reflect the pin assignments, and then I compiled correctly and uploaded to the board.
Then, following the design example instructions, I imported the project into eclipse, built successfully, and then ran the program in DS-5 Debugger mode. The program ran but stalled at a wait point in the debug file. Here is a snip of what appears in the command window:
Connected to running target Altera - Cyclone V SoC (Dual Core) cd "C:\[...]\CV_FPGA_to_HPS_Bridge_Design_Example\software\Altera-SoCFPGA-HardwareLib-FPGA2HPS-Bridge-CV-GNU" Working directory "C:\[...]\CV_FPGA_to_HPS_Bridge_Design_Example\software\Altera-SoCFPGA-HardwareLib-FPGA2HPS-Bridge-CV-GNU" source /v "C:\Program Files\DS-5 v5.29.3\sw\debugger\configdb\Scripts\altera_target_check.py" No SYSID registers could be found. Has a peripheral description file been supplied? source /v "C:\[...]\CV_FPGA_to_HPS_Bridge_Design_Example\software\Altera-SoCFPGA-HardwareLib-FPGA2HPS-Bridge-CV-GNU\debug-hosted.ds" +reset system +wait 30s Target has been reset Execution stopped in SVC mode due to a breakpoint or watchpoint: S:0x00000000 S:0x00000000 LDR pc,[pc,#24] ; [0x20] = 0xA8 +stop WARNING(CMD315): Target is not running +wait 30s +set semihosting enabled false +loadfile "$sdir/u-boot-spl.axf" 0x0 Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF6FE3 (size 0x6FE4) Loaded section .rodata: S:0xFFFF6FE4 ~ S:0xFFFF8E1F (size 0x1E3C) Loaded section .data: S:0xFFFF8E20 ~ S:0xFFFF9CF3 (size 0xED4) Entry point S:0xFFFF0000 +set semihosting enabled true Semihosting server socket created at port 8000 +delete All user breakpoints deleted +tbreak spl_boot_device Breakpoint 1 at S:0xFFFF1478 +run Starting target with image C:\[...]\CV_FPGA_to_HPS_Bridge_Design_Example\software\Altera-SoCFPGA-HardwareLib-FPGA2HPS-Bridge-CV-GNU\u-boot-spl.axf Running from entry point +wait
Why does the program just stop here? It is as if it does not find the breakpoint? Pressing the continue button does not do anything in Eclipse. I do not know how to address this problem, and I didn't change a lot from the design example, so I feel like it should work well unless I'm running it incorrectly.
Any help at all would be greatly appreciated! If I can get this example to work it would be so useful to me
- Cyclone® V FPGAs
- FPGA SoC And CPLD Boards And Kits
- Intel® SoC FPGA Embedded Development Suite
Please try any other example like hello world or FFT as given in the link below, so that we can be sure that
any edits like SDRAM settings edit or script changes are not causing this issue.
Thanks and Regards