Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21587 Discussions

Cyclone V Soldering Process

Binoyjohnson
Beginner
1,171 Views

Hi,

We are using cyclone V (5CSEBA4U23I7N) in one of the project. Is it recommended to assemble the SOC in the first reflow process?. Is there any problem, if the SOC pass through the second reflow it includes DDR as well, in terms of reliability. We are following the lead free reflow process.

Thanks Regards

Binoy Johnson 

Labels (1)
0 Kudos
5 Replies
NazrulNaim_Intel
Employee
1,155 Views

Hello,

 

To answer your request. For reflow profile, we follow the Industrial Standard – IPC/JEDEC: J-STD 020E or newer.

 

Regards,

Nazrul Naim


0 Kudos
Binoyjohnson
Beginner
1,131 Views

If you can answer with Industrial Standard – IPC/JEDEC: J-STD 020E a screenshot it would be great 

0 Kudos
NazrulNaim_Intel
Employee
1,066 Views

Hello,

Sorry for the delay. For your information the information for this one can be directly obtained from the JEDEC official website.


Hope that answers your question.


Best regards,

Nazrul Naim


0 Kudos
NazrulNaim_Intel
Employee
1,022 Views

Hi,

 

As we do not receive any response from you on the previous question/reply/answer that we have provided, for now I will set this case to Close-Pending. 

 

Regards,

Nazrul Naim


0 Kudos
Binoyjohnson
Beginner
1,005 Views

If you can arrange screenshot, it would be great. I couldn't get the information.

0 Kudos
Reply