Cyclone-V changing off-chip signal timing using IObuf delays

[Altera_Forum]

Because of routing differences in a bus system we want to experiment with input IO-buf delays of a cyclone.  

 The D3_delay and D1_delay options in the quartus assignment editor are available but I do not know their value range and units (sec/usec/??). Does anyone has info on this.   Performance improved when using FAST_INPUT_REGISTER assignment on the bus clock signal. Is this attribute the counterpart of D1/D3_delay or can these be combined?

[Altera_Forum]

Refer to the 'Programmable IOE Delay' section, page 81, in the "cyclone v device datasheet (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_51002.pdf)". 

 Cheers, Alex

[Altera_Forum]

You should use Fast I/O register assignment before resorting to buffer delays (which without looking at the document I think are usually in 50 ps increments). That makes the design use the input or output register located in the I/O block, the closest it can be to the I/O pin.

[Altera_Forum]

Thanks for the reference Alex. Do you also happen to know if these figures are the range or the step size of the parameters? 

 Sstrell do you mean the FAST_INPUT_REGISTER assignment? Can this one be combined with an input delay like D3?

[Altera_Forum]

I've always assumed, and used it as if, it's the range - although finding a statement to that effect eludes me. Timing analysis is your friend here. 

 Yes, you can use both together.  Cheers, Alex