Cyclone10LP Substrate Layers compared to Cyclone III

[DKolo]

From the past, severe simultaneous switching noise were seen on smaller Cyclone III’s (e.g. EP3C40) which weren't seen on the larger (e.g. EP3C120) ones.

Can you confirm that the 10CL120Y has the same number of layers as the EP3C120 and thus won’t see the issues that were seen on smaller Cyclone III parts?

[ChiaLing_T_Intel]

Hi,

According to AN731 document which applicable to Cyclone 10 LP, Cyclone IV, and Cyclone III devices showed that larger SSN is induced when there is multi-aggressor input/output signals toggle simultaneously. To limit SSN, you must restrict the number of switching outputs in a single bank. You can refer to the link below for more details:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an731.pdf

Thank you

Regards,

Chia Ling

[DKolo]

Hi,

I am aware of AN731, but is it possible to confirm how many layers the 10CL120Y has compared to an EP3C120?​

Thanks

[ChiaLing_T_Intel]

Hi,

Cyclone III transitioned from either 4à2 or 6à4 layers sometime back in 2010, including EP3C120:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/pcn/pcn0904.pdf

The SSN issue that were seen in Cyclone III applies to Cyclone 10, therefore you are recommended to follow the SSN guidelines as stated at AN731 document.

Thank you

Regards,

Chia Ling