DDR input without DPA in Arria II GX

[Altera_Forum]

Hello 

 I am using arria ii gx to communicate with a high speed device. The device is sending DDR data, data with a data clock, dclk. dclk and data are source synchronous. I need to capture the data inside my Arria II GX FPGA, using dclk and separate it into a positive & negative edge streams.   The problem is that the skew between dclk and data, by the time they get into the FPGA, is unknown. Thus I want to be able to slide dclk or try different phases of dclk to capture the data. I was able to do this in Xilinx Virtex FPGAs using the iobdelay function, which allowed me to adjust the skew between dclk and data at run time. I want to do exactly the same in Arria II GX but I find no comparable option. I do not have a training pattern so the dpa is out. Can someone suggest a solution? Can I gain the ability to try various phases of dclk for sampling data in Arria II GX?  Thanks in advance for your help!!!

[Altera_Forum]

There is a "DQS delay chain" in Arria II that you could use to adjust the phase between clock and data dynamically.

[Altera_Forum]

Thanks for replying!! 

 But "ALTDQ_DQS" is not supported in Arria II GX? At least that is what the megawizard data sheet says. "ALTMEMPHY" functions generates a whole DDR Memory controller which I don't want.  Any more suggestions?

[Altera_Forum]

What's the data rate? Can offer solutions until we know that. 

 Jake

[Altera_Forum]

Thanks for replying! 

 The device is sending data at 1 GHz with a 500MHz clock (DDR fashion). I want to split it into 4 streams of 250 MHz inside Arria II GX fpga.  I am exploring the suggestion of using alt_dq_dqs but I am not sure if I can provide a high speed clock to a DQS pin in Arria II (I am not sure if DQS pins are also routed to regional or global clock trees)  Please advice.  Thank!

[Altera_Forum]

Is the relationship between DCLK and DATA fixed on every board or does it change between boards. Meaning do you just need to determine the relationship once for the design or is every instance of the board going to have something different? 

 If it is static, you can control the skew with timing constraints.  If it is dynamic, One thing you can do is bring DCLK into a PLL. Then you can phase shift the PLL until you get the right sampling position.  Jake

[Altera_Forum]

Hello 

 Not only the relationship between data and clock, the input frequency of the clock also changes from board to board (max is 500 MHz). :mad: I think Dynamic PLL reconfiguration is an appealing idea, if it is available in Arria II. Thanks a lot for your guidance!  Any reference design that I can use?:D  Regards,

[Altera_Forum]

So the skew actually changes from board to board? And your frequency is unknown? 

 Well this is quite the interface you've got. A high-speed source-synchronous interface with absolutely no deterministic qualities.  What things are known about the interface that we can make use of?  Jake

[Altera_Forum]

Jake, 

 Its not that nothing is known. For each board, the frequency of the clock coming in as well as its relationship to the data bus is known; its just that both of these are changing from board to board. To create a separate bitstream for each board is not feasible, so my goal is to build a design in which I can vary the skew between data and clock before it gets sampled by the input DDR cells. Hit and trial by user (granted an ability to play around with the skew adjustment), until data is correctly sampled, is acceptable.   Thank you very much for your kind and generous help!

[Altera_Forum]

Is the clock always present such that it can be used as a PLL input?

[Altera_Forum]

Your question is partly based on wrong assumptions. DPA doesn't require a train pattern, it only requires signal edges to be present during the adjustment. Without signal edges, you can perform no adjustment at all. A train pattern is needed for adjustment of the SERDES bit slip feature (shifting by integer bit clock intervals), but you can also control it manually or disable it. 

 DPA does however need a PLL, and this also means implicitely a fixed frequency (respectively a small guaranteed lock range). So dynamic reconfiguration is necessary to achieve a wider frequency range. Instead of DPA, which is adjusting the receive phase automaticly (and keeping it on request), PLL dynamic phase shift is also available with Arria II. It allows a manual stepwise control of a clock phase.   Logic cell delay, variable e.g. through a multilplexer would allow a limited range, step wise phase adjustment without depending on a particular clock frequency. Logic cell delays aren't well specified and also temperature dependant, in so far they perfectly complement your loosely specified clock.  P.S.: IOBDELAY with Xilinx is, as far as I understand a constraint parameter, not variable at runtime.

[Altera_Forum]

Looks like both FvM and I have brought up the dynamic phase shifting of the PLL. I'm thinking that's what you ought to look into. Again though, you're going to have to be able to dynamically reconfigure. I'll again pose the question. Is the clock input always present? 

 Jake

[Altera_Forum]

Jake 

 The DDR clock and data from the device will come into the FPGA when the FPGA board is connected to the other board. However, I plan to run the FPGA using a clock from an on-board (FPGA board) oscillator.   That should not be a problem, right?

[Altera_Forum]

FvM 

 IDELAY in Xilinx allows delays in multiples of 50ps to be inserted in an I/O pad and that is what I meant. My apologies for using incorrect word.  Regard,

[Altera_Forum]

The Stratix IV does have programmable IO delays but Arria II GX does not.  

 Jake

[Altera_Forum]

Jake 

 I know Stratix has that feature. Unfortunately, I need to find a way of achieving it on Arria II GX.   The PLL dynamic phase change looks promising. But I will be limited to only 8 possible phases because M=1, N=1 would make the VCO frequency same as input frequency and thus I would loose the 'fine tuning' that would have been available if my VCO frequency were higher. Do you think the following scheme can work?  ** Use a PLL  ** PLL ref clock is DDR input clock ** PLL in normal mode ** M=N=1 ** PLL output clock is used to sample input data ** Use Dynamic Phase shifting inputs of PLL to move PLL output clock to optimum sampling position  Regards

[Altera_Forum]

That's what I would try. 

 Jake

[Altera_Forum]

Arria II does have dynamically configurable PLLs. 

 I'm not sure you could 500MHz through Arria II IO however?? Have you checked timing in Quartus? I'd be interested in knowing what the top speed is.

[Altera_Forum]

My comment on IOBDELAY wasn't related to your describing words. My point is, that it's apparently not programmable at runtime, so it wouldn't help for your application, I think. The same with programmable IO delay provided by some Altera chips. 

 The timing resolution of PLL dynamic phase shift is basically one VCO ring oscillator stage delay. The same granularity is in effect for DPA, if I understand it right. Because the VCO operating range is 600 ... 1300 MHz, the delay increment could be 125 ps at 1000 MHz VCO frequency. It's generally preserved when dividing the clock.  std_logic is right however that 500 MHz frequency isn't feasible for internal or external clocks with Arria II. You would have to run two 90° phase shifted 250 MHz clocks with two DDR receivers in parallel.  P.S.: There's another point I just came upon. I have taken as granted, that PLLs have a limited lock range around the specified center frequency. Looking at the parameters supplied in PLL reconfiguration, there's obviously no frequency related parameter except charge pump current, that sets the PLL loop gain. So it can be expected, that the VCO should be able to lock within it's full specified frequency range. Thus with suitable divider parameters, a 1:2 lock range would be possible.

[Altera_Forum]

Hello 

 IDELAY does allow delay settings at runtime; I have used it myself.  According to the Arria II datasheet, the PLL input frequency is 5-500 MHz .. the memories can goto upto 390 MHz .. The lvds inputs can easily swictch at 1 GHz .. so arria ii gx can be used to communicate with 1G device ..  The only thing to figure out is what is the best way to do it (with the ability to adjust skew between ddr data and clock at run time) ..  All suggestions are welcome

[Altera_Forum]

--- Quote Start ---  The lvds inputs can easily swictch at 1 GHz .. so arria ii gx can be used to communicate with 1G device ..  --- Quote End ---   1 GBPS LVDS is possible in DPA mode (because the DPA circuit is using it's own clock network), 945 GBPS in non-DPA mode, with fastest speed grade respectively So if you utilize DPA for your design, you can operate a SERDES at 1 GBPS, otherwise you can't (at least not by guaranteed specification). As said, DPA basically involves an automatic adjustment of receiver phase to the incoming data edges, but not setting a particular receiver phase manually.  In my opinion, several promising suggestions have been made. You should start trying the different options.  Regarding VCO lock range, I verified, that the about 1:2 range can be actually utilized with Cylone devices, it should also work with Arria II, that has a similar PLL specification. For a larger frequency range, dynamic reconfiguration would be necessary.  P.S.: Can you tell which XILINX devices have a runtime programmable IOBDELAY?