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DDR2 design compilation very long !

Altera_Forum
Honored Contributor II
‎01-26-2013 02:45 PM
1,159 Views

Hi, 

 

I'm currently trying to test a DDR2 (MT47H32M16 -25E) on a board but the compilation time is very very long... (more than 4 hours for a block diagram with only one PLL and a DDR2 SDRAM Controller with ALTMEMPHY. I thought the problem was about parameters I changed to have a custom design file for MT47H32M16 -25E but when I select a memory preset I have the same result. 

 

I already made some tests a few months ago on a cyclone IV GX evaluation board and the compilation was during about 10 minutes.  

There must be something wrong somewhere, but I have no clue where to look for solving this problem. 

 

If anyone have an idea, please tell me. 

 

Thanks.
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Altera_Forum
Honored Contributor II
‎01-28-2013 02:01 PM
476 Views

I think I found why it didn't worked. By deleting signal_tap block on the top design, the compilation take only 5 minutes.

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