Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21611 Discussions

DDR2 design compilation very long !

Altera_Forum
Honored Contributor II
‎01-26-2013 02:45 PM
1,158 Views

Hi, 

 

I'm currently trying to test a DDR2 (MT47H32M16 -25E) on a board but the compilation time is very very long... (more than 4 hours for a block diagram with only one PLL and a DDR2 SDRAM Controller with ALTMEMPHY. I thought the problem was about parameters I changed to have a custom design file for MT47H32M16 -25E but when I select a memory preset I have the same result. 

 

I already made some tests a few months ago on a cyclone IV GX evaluation board and the compilation was during about 10 minutes.  

There must be something wrong somewhere, but I have no clue where to look for solving this problem. 

 

If anyone have an idea, please tell me. 

 

Thanks.
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎01-28-2013 02:01 PM
475 Views

I think I found why it didn't worked. By deleting signal_tap block on the top design, the compilation take only 5 minutes.

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.