Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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DDR3 Hard IP problem (Cyclone V)

Altera_Forum
Honored Contributor II
‎05-07-2015 02:15 PM
1,041 Views

our design includes ddr3 hard ip, pcie hard ip and so on. we use CvP to update the fpga core logic, but after update the core, we cann't read and write ddr3 memory. 

 

please help 

 

thanks!
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Altera_Forum
Honored Contributor II
‎05-08-2015 11:37 AM
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anybody know why?

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