Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21616 Discussions

DDR4 VTT termination for ADDRESS/CONTROL - ARRIA10 HARD IP

LSOCH
Beginner
‎09-07-2020 01:31 AM
809 Views

Hi ,

if i have a single x16 DDR4 component connected to a ARRIA10  device and running at 800 Hz clock(1600 MT\S ) - is there a waiver that allow me to not have a VTT termination for the ADDRESS\CONTROL signals ?

Are you familiar with designs which have done that?

Thanks,

Lior

 

 

0 Kudos

Link Copied

1 Reply
yoichiK_intel
Employee
‎10-07-2020 10:14 PM
784 Views

You will need to run the Board simulation if you wish not to terminate the ADR/CMD to VTT.

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.