DE10 Lite FPGA internal RAM usage

[YigalB1]

Is it possible to fill a RAM IP within the FPGA of DE10 lite, after it was programmed, with MIF file using Quartus command line? And read it back to the host?

The idea is to generate time after time a MIF file at the host (using Python), write the data to the RAM inside the FPGA, and read the RAM content back to the host once the FPGA finished processing it. (the RAM content is modified during the process stage).

All without re-programming the FPGA.

[sstrell]

No.  It's only used as part of device programming or can be used for simulation.

Whatever you are using in your design to access the RAM should be used after device programming.

[YigalB1]

Ahh.. I start to understand:

I noticed that programming the .sof is valid until power down, while .pof is much longer and "forever" (or next programming).

Do you mean that the SDRAM is used to hold this .sof programming file until next power down? 

If so I may have another approach:

1- I assume this data can be overwritten after the FPGA was programmed, so it is not needed  after that moment.

2- What portion of the SDRAM is used for the FPGA?

3- Is it possible to manipulate the .sof file, and fill it with my data, following the FPGA programming required?

4- Is it possible to manipulate the programming process in this way: send the data to the SDRAM as if it is going to be programmed, but not program the FPGA? If so, the process can be: a) program the FPGA with .pof file (One time, long). b) Send manipulated .sof file, which will not be programmed, and then the FPGA will be able to use this content for processing the SDRAM content.

5- What is the process on the DE10 Lite after the SDRAM was programmed with .sof file? Where is the programming logic residing? How is it triggered after the .sof file is written to the FPGA? (is there a documentation for that?)

[FvM]

Hi,
there's no relation between MAX10 internal RAM and SDRAM on DE10lite board. Neither an option to hold FPGA configuration data in SDRAM.

Regarding internal RAM, you'll usually communicate with it at run time through custom design. There's also an "In-System Memory Editor" feature that allows to read and write internal RAM over JTAG.

[sstrell · Accepted solution]

No. .sof is for direct programming of the FPGA through JTAG. It’s not stored anywhere other than the computer you’re using to program the device. .pof can be stored in a flash (non-volatile) memory so the FPGA is configured automatically on power up. An SDRAM cannot store programming information because it is volatile, and the FPGA cannot access SDRAM until it is programmed because the programming sets up the controller and PHY needed to communicate with the external memory. So your questions don’t make sense. I’d recommend reading the programming/configuration chapter of your targeted device family for basic understanding of how FPGAs are configured and used.

[YigalB1]

It seems I wrongly understood the answer above " It's only used as part of device programming or can be used for simulation.". 

In this case it seems I can't use the SDRAM as a means of data transfer between the host and the DE10 Lite. Thank you all for answering.