Hello,I'm trying to build my first DE10 Nano design, and getting some critical fitter warnings that make no sense to me. Specifically, I get the "warning" that, "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details." Then I get the critical warning that, "No exact pin location assignment(s) for 75 pins of 138 total pins. ..." If I look up the "undefined" pins, many of them are HPS_DDR3xxx pins. If I try to assign these pins within the pin editor, I cannot. Instead, they have default locations (matching the schematic) that cannot be changed. There are other warnings as well, indicating that perhaps the DDR3 SDRAM wasn't set up properly, although at this point I have no idea what I might have missed. I've attached both my top level file, as well as the fit report showing the various I/O errors and warnings I've been receiving. Any suggestions? Dan
Absolutely!But did you notice that all of these pins are fixed on the Cyclone-V? Or, at least, I think that's what's going on. Quartus correctly accepts the pins for the normal I/O ports, but seems to ignore these ones. Indeed, I can't seem to get Quartus to accept any .qsf file with pin locations in it, such as the one I'm attaching now. (A .txt extension was added to allow the upload.) So ... I'm still stuck. Any suggestions? Dan
In your .qsf file you have lines like:
... set_location_assignment PIN_J15 DEFAULT -to HPS_ENET_GTX_CLK set_location_assignment PIN_A16 DEFAULT -to HPS_ENET_TXDATA set_location_assignment PIN_J14 DEFAULT -to HPS_ENET_TXDATA ...What gives with the word default in the command? I have never seen that usage before. Can you remove the default keyword from all those lines?
Yeah, okay. The "DEFAULT" was placed in there after it didn't work without it. (It didn't work with it either---I've tried a lot of things, nothing has worked. What works for setting the switch and LED pins, doesn't work for setting these last pins--hence the post in the first place.)It's been suggested to me that this error will *always* occur on the hard-wired pins of the Cyclone-V (HPS+FPGA). I'm going to try to ignore it and see what happens. Dan
If your design doesn't use the DDR3 IP, you can ignore these warnings. Even when I did a sample design with just simple logic, the fitter would spit out warnings that some DIFF IO pins are not assigned,but the compilation and other processes would go on successfully.Just make sure that all of the other processes do not have any errors and that the final stages are all clear. You can ignore these if you're not using them in the design.