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Hi,
I am engg student.I are working on SOPC baesd speech to text conversion.I am confused with how to to program audio codec for Audio to Digital conversion for input from microphone and give it to FPGA.Link Copied
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i am looking module for my project too
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Hi,
I'm not quite sure, but I think you can use the SPI SOPC module to build up the communication path to the CODEC Chip. . . . Maik- Mark as New
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i use Audio Codec but i dont understand how it config
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Hello, I am attaching a VHDL file which describes an interface to the Wolfson WM8731 Audio Codec chip located on the Altera DE1 and DE2 boards. This version just does output, but you can augment it to do input. For this you will have to read over the WM8731 datasheet.
I have tested this on both the DE1 and DE2 boards. I hope you find it useful, but there is no warranty implied! Jim- Mark as New
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--- Quote Start --- Hello, I am attaching a VHDL file which describes an interface to the Wolfson WM8731 Audio Codec chip located on the Altera DE1 and DE2 boards. This version just does output, but you can augment it to do input. For this you will have to read over the WM8731 datasheet. I have tested this on both the DE1 and DE2 boards. I hope you find it useful, but there is no warranty implied! Jim --- Quote End --- thanks for sending the VHDL code ,this code utilise the clock of 24Mhz i have 50 MHz crystal in my DE2 board so please suggest the change in the code thank u again
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Hello Mr. Khan, you could use one of the PLLs on the Cyclone II chip to convert from 50MHz to 24MHz. Or you could just implement a simple counter. You could just divide by 2 (giving 25MHz). This would result in a sampling rate slightly more than 48KHz, but depending on your application would probably not make an audible difference.
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--- Quote Start --- Hello Mr. Khan, you could use one of the PLLs on the Cyclone II chip to convert from 50MHz to 24MHz. Or you could just implement a simple counter. You could just divide by 2 (giving 25MHz). This would result in a sampling rate slightly more than 48KHz, but depending on your application would probably not make an audible difference. --- Quote End --- Dear sir i have done the intitialization of the codec registor by using the 50Mhz crystal i am getting ack , sir i am not getting whether xclk i.e the master clock of codec must require to fetch the data from LR chanal please sugest the logic for sound fetching & more about the DSP mode of codec.
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Hello, you should read the WM8731 datasheet. All the details you need are in there.
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--- Quote Start --- Hi, I am engg student.I are working on SOPC baesd speech to text conversion.I am confused with how to to program audio codec for Audio to Digital conversion for input from microphone and give it to FPGA. --- Quote End --- Go throw the data sheet of codec configure the codec registor ,the sound digital data will be available on ADCDAT of codec
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Thanks for your vhdl code jjclark. It is really helpful.
I have set it up and it works perfect. I am now trying to feed line in from the audio codec. But am having trouble, as the output has a lot of noise. Im guessing its got something to do with my timing? Would you be able to attach an example of line in? That would be very appreciated.- Mark as New
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Would be nice if guys can attach the file for the linein, i have been trying to do it, and just can't.. I have read the datasheet... Thank You.
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--- Quote Start --- I have tested this on both the DE1 and DE2 boards. --- Quote End --- Hi, I am wondering how you tested it. Did you send random values on your data lines? I'm trying yo used this code on a different development board but the principles are the same. Regards, Hunter
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Good Day Everyone
The g00_audio_interface.vhd code does not process the input of audio, as stated in the pretext information. Does anyone know how the input can be done? (in VHDL code) Kind Regards- Mark as New
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--- Quote Start --- Good Day Everyone The g00_audio_interface.vhd code does not process the input of audio, as stated in the pretext information. Does anyone know how the input can be done? (in VHDL code) --- Quote End --- I also need to know how. should you find help elsewhere, please let me know n I sure will do the same... Kind Regards
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Good day
I still have not found it out. My development board (altera cyclone II) passes the input(linein) straight to the output (lineout) irrespective of the bypass setting. Does anybody know how to prevent the input displaying on the output.- Mark as New
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Thank you . It's what i finding .
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Hello.I'm new here.Soo I have to work on a project that needs to analize music frequency and display it on the leds on the DE2.My question is : How do I use the DE2 to turn music into analazible data?
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hi i am having same trouble i need to use the line in or mic in as well can anybody help in that whatever i do the sound gets output automatically how to control it???
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Thanks.. I think this will be very helpfull since i need to use Audio Codec in De2 board.
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--- Quote Start --- Hello, I am attaching a VHDL file which describes an interface to the Wolfson WM8731 Audio Codec chip located on the Altera DE1 and DE2 boards. This version just does output, but you can augment it to do input. For this you will have to read over the WM8731 datasheet. I have tested this on both the DE1 and DE2 boards. I hope you find it useful, but there is no warranty implied! Jim --- Quote End --- Maybe you could explain to newbie why the code is designed for a 24MHz clock. Doesn't both DE1 and DE2 have 50MHz and 27MHz clocks?

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