DMA Controller with external DREQ/DACK mechanism on CPLD or FPGA

[Zaher]

Hello everyone,

I've been working with microcontrollers for quite some time now. I have never used a CPLD or FPGA for any of the projects I worked on. I don't know why the idea seems intimidating for me, but it's been of a great interest to me for so long.

The project I'm working on involves a legacy ASIC that requires a DMA controller similar to Intel's 8237 with external DREQ/DACK mechanism, which is not available on most microcontrollers available in the market today.

If a CPLD or FPGA can fill the gap for me and replace the microcontroller, I would be glad to consider one for the project concerned. Basically, the microcontroller interfaces with the ASIC via parallel interface and provides some basic functionality like LED switching, USB, and SDIO.

Any comment is highly appreciated!

Zaher

[Hazlina_R_Intel]

Hi,

Thanks for your question. You may check out this white paper:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01041-six-ways-to-replace-microcontroller-with-cpld.pdf

It made references to some very old CPLD products that we have but the basic principles still apply.

For the list of the newer CPLDs, you may visit this page:

https://www.intel.com/content/www/us/en/products/details/fpga/max.html

-Hazlina

[Zaher]

Hi Hazlina,

Thank you very much for your prompt reply. That old white paper was a great reference for me. The CF+ to uC interface is one of the applications I have in mind for a project.  I wanted to do bridging between ATA/IDE and another bus and the CPLD as a companion to uC seems a best fit for that application because CF is implemented in true IDE mode. I believe the merger between ALTERA and Intel makes it indispensable source for any designer who wanted to tap into a plethora of design examples without them reinventing the wheel. It seems diving into the world of programmable logic is inevitable for me.

Well, I didn't see any reference to the DMA controller implementation on a CPLD or FPGA in the white paper. Anyways, in reference to AN495 (IDE/ATA controller) on MAX 10 series, the scenario I have in mind is to use the Nios II embedded processor IP core in addition to the IDE/ATA controller core and the DMA controller core in one single device without a microcontroller. However, I'm still unsure if this scenario is possible and whether I can achieve the DMA controller aforementioned above with proper DREQ/DACK signaling so I can use it to move data between the ASIC and the microcontroller.

Any comment is highly appreciated!

Zaher

[Zaher]

Could you please provide valid download links for the following:

http://www.altera.com/literature/an/an492_design_example.zip

Also, I could not find example for the compact flash interface (same application note 492) on Max 10 on at the Design Store

[Hazlina_R_Intel]

This is the latest link for AN492: https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/compactflash-interface-an-492/?wapkw=an492 

We have other design examples in our Design Store here: https://fpgacloud.intel.com/devstore/

For DMA controller IP you may refer to the brief here: https://www.intel.com/content/www/us/en/secure/design/internal/content-details.html?DocID=618538

On your question on the feasibility to use Nios II embedded processor IP core in addition to the IDE/ATA controller core and the DMA controller core in one single device without a microcontroller, let me get an engineer to assess this for you. 

-Hazlina

[Zaher]

Thank you very much for the follow up. I have downloaded the material available for AN492 on the link you provided. I have been to the Design Store, but I didn't see any examples for ATA/IDE controller or CF card interfacing. If you are referring to examples for these particular applications, please provide links to those examples.

Unfortunately, I couldn't access the resource for the DMA controller IP on the link you provided. It has requested extra privileges and a CNDA. I made the request, but not sure whether or when it would be approved so I can access that resource.

It would be great if you can get some feedback from one of your engineers about the scenario I have in mind.

Regards,

Zaher

[Zaher]

It looks like I have downloaded the standard version of Quartus Prime that requires a paid license. I have removed it and now installing the Lite version on Ubuntu 20.04. The installer didn't terminate properly for the standard version so I was wondering if there are any known issues installing the Lite version 16.0 on Ubuntu 20.04. I don't know if you suggest working with the latest version of Quartus Prime software, however, the example I want to build my project around is only supported by version 16.0 (AN 495). I believe same applies for CF+ interface example.

[Zaher]

Just a quick update, it would be great if you can provide me with AN 495 example files for the Max II devices.

I look forward to hear back from you regarding your engineer's assessment for my intended application.

[EricMunYew_C_Intel]

You can refer to below reference:

https://fpgacloud.intel.com/devstore/platform/15.1.0/Standard/max10-10m50-development-kit-ghrd-with-nios-iiddr3qspi-flashethernetmsgdmauartadc-with-linux/