Data Transfer from FPGA-to-HPS

[Altera_Forum]

Hi Everyone, 

 To give some background here is what I am currently working on, what hardware I have, and what I am trying to implement to solve my issue. Board: DE0-Nano-SOC 5CSEMA4U23C6  Issue: I will be receiving around data into the FPGA at 40MHz. I need to make this data available to the HPS. The data will be ready in around 37KB chunks, I am planning on using a double buffer system so say we need a 75KB space to store said data. My idea is that I will stream the data in, fill up the buffer, signal the HPS that it is ready, the HPS will read the data, package it, and send it over an Ethernet network. I have actually asked this question in another part of the forum here: https://alteraforum.com/forum/showthread.php?t=58944&p=239654#post239654, but realized this section would be better suited to the question. Going off what was talked about there, I am trying to get the FPGA-HPS bridge working in order for the FPGA to write to the HPS's DDR3 RAM and then have the HPS read from it. I have set the board up from the QSYS side correctly I believe. I limited the HPS RAM for linux to 800 MB. Then I have been trying to write to address 0x32000000, with absolutely 0 luck in getting anywhere. I am not sure if I am setting up something wrong in Quartus, my C code, or some other issue. And would appreciate any assistance in this.  Thanks! -Andrew  EDIT: Currently I am using Linux, but I would eventually like to move to BareMetal, for now though I am sticking with Linux.

[Altera_Forum]

Can you add some signaltap probes around your master, to check that it is actually writing to the memory? 

I have never developped on embedded with Linux, but basically you shoudln't need to limit the ram available to the operating system. Just allocate a block of memory (aligned with data cache lines), obtain it's real physical address (if you are using an MMU) and have your hardware write to it. Once it's done, don't forget to invalidate the data cache before accessing the data from the software.

[Altera_Forum]

--- Quote Start ---  Can you add some signaltap probes around your master, to check that it is actually writing to the memory? I have never developped on embedded with Linux, but basically you shoudln't need to limit the ram available to the operating system. Just allocate a block of memory (aligned with data cache lines), obtain it's real physical address (if you are using an MMU) and have your hardware write to it. Once it's done, don't forget to invalidate the data cache before accessing the data from the software.  --- Quote End ---    I'll have to look into the SignalTap part, I think that's been a big part of my issue is not really knowing where things are going wrong since I'm not exactly an expert on how to use Altera's tools. Also for anyone else that happens to have similar issues to mine I forgot to set the byteenable bits, so that is at least part of my issue. I'll look into what you were saying about the memory part as well. Would you happen to have a guide or anything for more info on that? Or would that be a better question for the software side of the forum?

[Altera_Forum]

Yes try in the software forum. Ihave no experience doing this with Linux as the embedded OS so I can't help you there