Data between gated clk's

[Altera_Forum]

Hi, 

I have a design that needs to use gated clk's in order to reduce the power consumption. I try to avoid using any speciel cells or PLL's, because I'm going to port it to an ASIC later on - but for verification I would like to try it in a FPGA first.  My problem is... I got a CLK_1 which is the master clk. This clk is feeding some high level blocks. I then gate it to CLK_g which feeds some blocks firther down in the design. When I run a synthesis I gets the error message about timing requirements are not fullfilled. If I set the 'Optimize hold timing' to all paths I don't get the error messages.  How can I verify that the timing is ok - I can't see any diffference in my simulations? When I look at my waveforms it doesn't look very nice - the gated clk changes from '0' to '1' 0.5 ns before the data pins changes. If I compare CLK_1 and CLK_g there is a delay of ~6 ns through my AND gate - that seems like a lot. Is it possible to delay the CLK_1, so the 2 clock are more alike?  Any advice is greatly appreciated.

[Altera_Forum]

Gated clocks are undesirable in FPGAs for several reasons, however I understand why you are doing this. As you discovered, they often create hold time violations. If you must use them, then turning on 'Optimize Hold Timing' to All Paths should fix the problem as you discovered, however it does this by increasing the routing delay of the data path to the destination register(s). This is better for timing analysis than adding a similar delay to the source clock (by manually adding a gate). You can verify that the timing is met by looking at the path in TimeQuest before and after making the setting to All Paths. You will see the increased routing delay to the destination register.

[Altera_Forum]

Thank you for your reply. I'm actually very glad you can see the purpose :) I thought I would be able to make the 2 clk's similar in time, but as I understand it changes the hold time for the data signals instead. 

 Thx again.

[Altera_Forum]

FPGAs have dedicated clock routing resources, which are great for distributing the clock in a low-skew manor, but their actual delay is pretty slow. So when your gated clock is created by getting off the first clock tree, going through logic, then back to a global buffer and through the clock tree, the imbalance can be quite large. Plus there is no way to easily add symmetrical delays to the first clock tree. All of these are quite easy in an ASIC. 

For FPGAs, it is generally recommend to create a clock enable instead of a gated clock to get the same functionality. That won't be a power savings though, since you're disabling the clock at all of its destinations rather than at its source. Technically you could write the code to have two implementations, one that gates the source for the ASIC and the destination's clock enable for the FPGA. In most cases that's probably not practical. One thing that might be beneficial is the altclkctrl block. It has an enable signal. You can instantiate the clock to go through multiple altclkctrl blocks and they will all be nicely aligned. (I'm not sure what device you're targeting, so look for it's architecture in the handbook). You can't do a ton of clocks this way, but if there are a few major ones, it might work.