Decrease system clock frequency in Quartus II?

[Vladislav-Butko-bvo]

How to decrease system clock frequency in Quartus II from standard 50 MHz to 2 Hz (two clock fronts per second)?

I find out it easier using constraints editing way, namely, SDC (Synopsys Design Constraints) file editing. But, don't know how do it exactly.

I work in Quartus II 9.0 (Build 132 02/25/2009 SJ Web Edition) and use the device Cyclone III (EP3C16F484C6) is placed on the Altera DE0 Board.

Was tried changing of the TimeQuest settings: was uploaded SDC file containing the line: "create_clock -period 500 [get_ports my_clk]".

[Vladislav-Butko-bvo · Accepted solution]

SDC rules don't affect on design. The FPGA hasn't own clock divider circuits. For frequency dividing need to impelement own divider circuit.