Hello all,
I'm currently developing a project with a display driving IP-core supplied by a manufacturer. The IP-Core utilizes two PLL's for DDR2 memory, while I also use one PLL for LVDS deserializing. The two PLLs used for DDR2 memory use both the same clock that is fed in by a dedicated clock pin, this however leads to a problem.
The (dedicated) clock that should feed both PLLs is routed global to both PLLs. Consequence is that the routed paths to the PLLs are not compensated, because of this i can't achieve timing closure.
The clock that should feed into these PLLs is connected to a dedicated clock pin (CLK7..4), and is feeding PLL2 and PLL4. According to the Cyclone 3 handbook Chapter-5 Figure5-2 The clock should be able to feed both the PLLs WITHOUT Being routed as a global clock. The clock is not used for anything else except feeding the two PLLs. Quartus also gives me a critical warning, that the PLLs are not driven by a dedicated clock and that this can cause issues.
I'm developing for the Cyclone 3 family (ep3c16 and up) and I am using Quartus 10.1 SP1 full version (for compatibility with IP-Core). How can i keep this clock from routing globally to the PLLs?
