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Default Value for Bidirectional differential signal

Altera_Forum
Honored Contributor II
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Hey everyone, 

 

I am creating a parametrized project which synthesizes a DDR2 controller only when the user specifies it is needed via a generate statement. There are 2 differential clock pins which are SSTL-II Differential output standards. I would prefer not to change this standard when the pins are not being used, and wanted to assign the signal default to a TRISTATE when the DDR2 controller is not being generated. 

 

Unfortunately, when tristating the signal in question, I get an error from the fitter stating that a bidirectional differential signal MUST use an output enable. I can understand this is good check for most cases, but how is defaulting the signal to a tristate not a valid assignment? The output enable is being used, since it is always disabled.  

 

To fix this, I created an always disabled ALT_IO_BUF, but I am guessing the synthesizer is just translating it to a tristate assignment anyways, so the fitter throws the same error. 

 

Any ideas? 

 

Thank you.
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Altera_Forum
Honored Contributor II
661 Views

Don't you have tristate option of unused pins in the project settings?

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Altera_Forum
Honored Contributor II
661 Views

Thanks for the reply. 

 

Yeah I have that set. I get the same error even if I don't assign anything to those pins. I think that the synthesizer just creates the same net (pin <= 'Z') which the fitter doesn't like.
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Altera_Forum
Honored Contributor II
661 Views

I am a bit unsure what actually you want or why. Unused pins (all) have options such as (as inputs tristated, ...etc) and you can choose whichever. But it has to be unused, so no logic connected to it.  

 

If you want unused pins to be other than that but you only want those pins to be tristated then you can apply 'Z' permanently.  

 

If you want to keep it bidirectional and I don't see why you can use a dummy select input for output enable, I mean use an unused input to do that selection and fool the tool
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Altera_Forum
Honored Contributor II
661 Views

How exactly do I interface with a differential signal that has a Single-ended Buffer for Differential-XSTL Input assignment? Everything I try fails.

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