Deserializers in Agilex 3 series

[UMall1]

I have a design that includes a Deserializer - originally designed for a Cyclone III device - that I want to import to an Agilex 3 device. The deserialization factor in my design is 10 see attached image. How do I import this Deserializer to the Agilex 3 device. Agilex 3 as far as I understand does not support deserialization factors of 10 (x1, x2, x4 to x8) supported. Do I understand the Agilex datasheet correctly - it does not allow deserialization factor of 10. I do not at this time have access to Quartus Prime and I therefore cannot see in software what options are available in the chip.

[FvM]

Hi,
there should be no problem to implement the functionality of original Cyclone III altlvds_rx IP in Agilex 3 fpga fabric without dedicated serdes IP because Cyclone III altlvds_rx hasn't advanced serdes features like DPA or CDR. Limitation of Agilex 3 and Agilex 5 serdes shows however when you try to port industry standard interfaces like receiver for 8b10b encoded data with CDR from Cyclone 10 GX or Arria 10.

Regards
Frank

[UMall1]

I do not believe I understood your answer very clearly. Do you mean that the Agilex 3 device will not be able to implement the x10 deserialization factor?

Is the MiPi interface also limited to 8b deserialization?

UM

[FvM]

I was referring to Agilex 3 serdes limitations mentioned in your post and meaned to say that the Cyclone III equivalent functionality can be achieved without dedicated serdes IP.

[UMall1]

How?

[ShengN_Intel]

Hi,

The Agilex 3 lvds serdes factor had been confirmed support 4 and 8 only. So if port the altlvds rx ip to Agilex 3, can only use 4 and 8.

[UMall1]

I thought the Deserialization factor can span a number between x4 - x8 - as seen in the image below (Taken form theAgilex3 datasheet).

How does Altera suggest a 360Mhz, x10 bit deserialization factor, 5-Lane SerDes be implemented in the Agilex 3 device? I do not think I am reaching the right people for support. Can someone forward the request to someone who specializes in SerDes circuits in the Agilex 3 device.

UM

[ShengN_Intel]

Hi,

Agilex 3 lvds serdes only has x4 and x8 serdes factor. If you check datasheet and i screenshot the ip settings as below (had been confirmed among lvds team):

https://www.intel.com/content/www/us/en/docs/programmable/848370/current/lvds-serdes-specifications.html

How does Altera suggest a 360Mhz, x10 bit deserialization factor, 5-Lane SerDes be implemented in the Agilex 3 device?

Do it with an x8 deserializer. Deserialize each lane by 8. Line rate = 360 MHz × 10 = 3.6 Gb/s (SDR). Line rate = 360 MHz × 10 = 3.6 Gb/s (SDR). Parallel rate after ÷8 = 3.6 Gb/s ÷ 8 = 450 MHz byte (8-bit) clock/domain. Feed the 360 MHz source-synchronous clock into an IOPLL and outputs with 360 MHz = your final 10-bit symbol clock (core domain) while 450 MHz = the x8 parallel domain for the SERDES output. Ratio is 450/360 = 1.25 (fractional PLL). Keep both clocks phase-related.

We have clock crossing adapter type to adapt the CDC https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/interconnect-requirements.html