Design Size and the timing accuracy

[Altera_Forum]

Dear Sir, 

 I've met one problem. It is about the design size and timing accuracy. If I have a design which used up the FPGA 95% or above LEs, is it going to have some I/Os having worse timing which may violate the requirements? Suppose, the answer is 'yes', because it is limited by the available resources. What I am going to ask is how to efficiently  manage the available LEs to meet the requirements? Is setting timing constraints in SDC file a goody way? In a case of no improvement, after changing the contraints, does it mean the available resource and path is used up? Thank you in advance.   Regards,     Peter Chang

[Altera_Forum]

--- Quote Start ---  Dear Sir,   I've met one problem. It is about the design size and timing accuracy. If I have a design which used up the FPGA 95% or above LEs, is it going to have some I/Os having worse timing which may violate the requirements? Suppose, the answer is 'yes', because it is limited by the available resources. What I am going to ask is how to efficiently  manage the available LEs to meet the requirements? Is setting timing constraints in SDC file a goody way? In a case of no improvement, after changing the contraints, does it mean the available resource and path is used up? Thank you in advance.   Regards,     Peter Chang  --- Quote End ---    HI Peter,  at first you need a proper SDC file. You have at least to constrain you Inputs, Outputs and clocks. This is important, because the constrains are used by Quartus for implementation of your design.   Kind regards  GPK

[Altera_Forum]

Dear GPK, 

 Thanks for your comment. I believe SDC is important for the timing constraints. However, is it possible that the requirements of my design are over that FPGA could provide in timing, especially while the available LEs are less.   Regards,     Peter Chang

[Altera_Forum]

--- Quote Start ---  Dear GPK,   Thanks for your comment. I believe SDC is important for the timing constraints. However, is it possible that the requirements of my design are over that FPGA could provide in timing, especially while the available LEs are less.   Regards,     Peter Chang  --- Quote End ---    Hi Peter,  of course it could be more difficult for Quartus to implement your design when the uitilization is high. You mentioned that you have mainly I/O timing problems. Can you explain it a little bit more ? Maybe I would help when you register your inputs and outputs by using the registers in the I/O cells.   Kind regards  GPK

[Altera_Forum]

Dear GPK, 

 Thanks for your explaination. The problem was found in a project which uses a FPGA MAXII micro to drive an external a LCM through an I2C interface designed via the I/Os. I've tried several times. When the design size larger, the timing of output signal is going to be wrong. For some test pins, even  the outputs are incorrect. I feel strange. Thus, I think the problems were caused by the limited resource in the FPGA. :) Regards,     Peter Chang

[Altera_Forum]

--- Quote Start ---  Dear GPK,   Thanks for your explaination. The problem was found in a project which uses a FPGA MAXII micro to drive an external a LCM through an I2C interface designed via the I/Os. I've tried several times. When the design size larger, the timing of output signal is going to be wrong. For some test pins, even  the outputs are incorrect. I feel strange. Thus, I think the problems were caused by the limited resource in the FPGA. :) Regards,     Peter Chang  --- Quote End ---    Hi Peter,  is it possible that you post your project ?  Kind regards  GPK

[Altera_Forum]

Dear GPK, 

 My design has been simplified to fit the FPGA. To post the original design, it takes time. I'll try to review my code, and then post it after. Thank you!   Peter