Design flow problem with PCIe IP

[Altera_Forum]

Hello, 

 I'm working on a PCIe design. However there're different design flows, such as Megawizard and Qsys, and different IP interfaces(avalon MM and ST). I'm new to both Qsys and PCIe. My FPGA design's function is mainly transmiting data to PC. Which flow and interface is better?  I read the application note which introduces an example design with Qsys. I haven't see anything about Nios II processor. Is it necessary for a Qsys design?  Best Regards, Cycad Hsu

[Altera_Forum]

If you use the latest Quartus 15.1, there is not Megawizard flow anymore. Everything is done thru Qsys.

[Altera_Forum]

--- Quote Start ---  If you use the latest Quartus 15.1, there is not Megawizard flow anymore. Everything is done thru Qsys.  --- Quote End ---    Is Nios II processor required in Qsys flow design?

[Altera_Forum]

>>> Is Nios II processor required in Qsys flow design? 

 Yes