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Devide in VHLD

Altera_Forum
Honored Contributor II
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I want to implement this function : A<= B/x"A", when I compile, the Quartus put a notice: "/" used but didn't declare. 

When I try with "*" (multiply) or "+" (add), it is ok. 

I don't know this error, Please help me. 

Thank you very much.
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Altera_Forum
Honored Contributor II
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two methods: 

 

1. result <= (not result) + 1; 

2. (probably easiest) result <= -result; (this will probably result in the same hardware as above when synthesised).
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Altera_Forum
Honored Contributor II
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And if you need more information about how to represent negative numbers in binary, this page from wikipedia (http://en.wikipedia.org/wiki/two's_complement) should answer your questions.

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

two methods: 

 

1. result <= (not result) + 1; 

2. (probably easiest) result <= -result; (this will probably result in the same hardware as above when synthesised). 

--- Quote End ---  

 

Oh. It's so easy but I don't find out. Thank Tricky very much. 

Thanks Daixiwen for your usefull information.
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Altera_Forum
Honored Contributor II
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Dear Tricky and Daixiwen 

Could you check this code for me? 

When I simulate by waveforms vector of Quartus, at Result_out, the final result is true but I have a lot of result 

Ex: (-30)x(-6) = 180 but I saw, they have 16, 148, 180. (I attached this waveforms in this message) 

I don't know this value. 

Thanks before. 

library IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.all; Entity Multvhdl is Port ( A,B : In Signed(15 downto 0); --A*B Result_out : Out Signed(31 downto 0); CLK : In std_logic); end Multvhdl; Architecture structural of Multvhdl is Signal Multiplicant,Multiplier : Signed(15 downto 0); Signal Result : Signed(31 downto 0); Signal CNT : unSigned(3 downto 0); Signal Sign : unSigned(1 downto 0); Begin Process(clk) Begin if clk='1' and clk'event then cnt<=cnt+"1"; sign<="0" & (A(15)xor B(15)); --Check sign of A and B if cnt="0000" then Multiplicant<= ABS (A); Multiplier<= ABS (B); elsif cnt="0001" then Result<=Multiplicant*Multiplier; elsif cnt="0010" then if sign = "00" then Result_out<=result; elsif sign = "01" then Result_out<= -result; end if; cnt<="0000"; end if; end if; end process; end structural;
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Altera_Forum
Honored Contributor II
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Alt first sight, the result_out waveform seems not to fit the above design (it may be still possible under specific conditions). result_out is a registered signal, clocked by the 100 MHz clock, but it changes shortly before the next rising edge, usually causing a setup violation for the following logic. Without knowing the previous states of all signals, and the timing constraints in effect, I can only guess about the reason for this behaviour. 

 

I also don't understand the purpose of the strange method to do a signed multiplication. The ABS() function is by the way causing an overflow for the most negative number -32768 (0x8000), which hasn't a corresponding positive value. 

 

P.S.: I see, that a similar negation method has been used previously in the thread. It may be a workaround for algorithms, that aren't avaliable for negative numbers for some reason. But multiply is.
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Altera_Forum
Honored Contributor II
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Dear FvM 

I want to implement Multiplication command in VHDL. Because Modelsim does not support for LPM library. And when I use multiply command directly, the result's not true with the negative number. 

In this method, I multiply two positive number, and use sign<=A(15)xor B(15); to check the sign of A and B. 

If sign=0 => the result's positive. else the result's negative. 

When I simulate with the waveforms, it appear strange value. I did not understand it. 

Do you have other idea for this?
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Altera_Forum
Honored Contributor II
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The output is not valid until CNT is 2 anyway, so until then all signals are rubbish.

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Dear FvM 

I want to implement Multiplication command in VHDL. Because Modelsim does not support for LPM library. And when I use multiply command directly, the result's not true with the negative number. 

In this method, I multiply two positive number, and use sign<=A(15)xor B(15); to check the sign of A and B. 

If sign=0 => the result's positive. else the result's negative. 

When I simulate with the waveforms, it appear strange value. I did not understand it. 

Do you have other idea for this? 

--- Quote End ---  

 

 

 

You can precompile most libraries in Modelsim. 

Usually altera_modelsim will have these lpm/altera_mf libraries ready from installation. 

Otherwise you can precompile as follows: 

go to modelsim => compile => set library name to lpm => navigate to altera folders that contain 220pack.vhd/220model.vhd. select them and compile.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

The output is not valid until CNT is 2 anyway, so until then all signals are rubbish. 

--- Quote End ---  

 

 

Thank Tricky. 

I had check this many times but I still did not know why the output have a lot of value. When I use this utility as a component for my project, the waveforms not nice.  

When i multiply -400x8, the final value still ok. but there are more than 10 strange value before the final value. (I attached waveform in this message) 

I don't know how to correct it.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

You can precompile most libraries in Modelsim. 

Usually altera_modelsim will have these lpm/altera_mf libraries ready from installation. 

Otherwise you can precompile as follows: 

go to modelsim => compile => set library name to lpm => navigate to altera folders that contain 220pack.vhd/220model.vhd. select them and compile. 

--- Quote End ---  

 

 

Thank Kaz 

I had done that a lot of time but it still error (Modelsim said, they do not found lpm library). I will make it step by step and send it to you, i hope you check it for me. Thanks again
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

The output is not valid until CNT is 2 anyway, so until then all signals are rubbish. 

--- Quote End ---  

 

Valid result or not, a registered output can't change arbitrarily. Or the design's timing is completely broken. 

 

--- Quote Start ---  

Because Modelsim does not support for LPM library. And when I use multiply command directly, the result's not true with the negative number. 

--- Quote End ---  

 

Last time I used it, all LPM libraries simulated fine in ModelSim. Sorry, I also don't understand about the negative number problems. At least, I wasn't aware of it (since Quartus V2.0).
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

 

Last time I used it, all LPM libraries simulated fine in ModelSim. Sorry, I also don't understand about the negative number problems. At least, I wasn't aware of it (since Quartus V2.0). 

--- Quote End ---  

 

Really? 

LPM library took me a lot of time. I use Modelsim plus 5.7d and Quartus 7.2 

Could you help me step by step with it?
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Altera_Forum
Honored Contributor II
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All Quartus specific libraries (LPM and device specific) have been installed during initial ModelSim installation (some ModelSimDE6.1 or 6,2 version). Unlike when simulating Verilog, I don't remember missing library issues with VHDL designs. But I don't have ModelSim installed on my computer now and can't check these problems. 

 

An additional remark related to your previously posted waveform. You didn't ever mention a device family. The timing could be explained if either belonging to a very slow logic family, or if the synthesis options in effect would allow to move an output register.
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Altera_Forum
Honored Contributor II
1,901 Views

 

--- Quote Start ---  

You can precompile most libraries in Modelsim. 

Usually altera_modelsim will have these lpm/altera_mf libraries ready from installation. 

Otherwise you can precompile as follows: 

go to modelsim => compile => set library name to lpm => navigate to altera folders that contain 220pack.vhd/220model.vhd. select them and compile. 

--- Quote End ---  

 

 

I don't know, why menu compile of my Modelsim software is not active. I can not choose it.  

I add 220pack.vhd/220model.vhd to my project and compile => not ok 

I can not make new library from "a new library and a logical mapping to it" or "a map to an existing library" to folder that contain 220pack.vhd/220model.vhd file. 

This is my video: 

Add 220pack.vhd/220model.vhd to project and compile them: http://www.mediafire.com/?44i1sj5bgnkduty 

Can not make new library: http://www.mediafire.com/?53zp5xyrpd2zdjk 

Can not make new library: http://www.mediafire.com/?krc4l1g5u5uyayj 

Could you check it for me. 

Thank alot
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Altera_Forum
Honored Contributor II
1,901 Views

 

--- Quote Start ---  

All Quartus specific libraries (LPM and device specific) have been installed during initial ModelSim installation (some ModelSimDE6.1 or 6,2 version). Unlike when simulating Verilog, I don't remember missing library issues with VHDL designs. But I don't have ModelSim installed on my computer now and can't check these problems. 

 

An additional remark related to your previously posted waveform. You didn't ever mention a device family. The timing could be explained if either belonging to a very slow logic family, or if the synthesis options in effect would allow to move an output register. 

--- Quote End ---  

 

I'm sorry when i forgot mention a device family. 

I use DE2-70 (Cyclone II) - EP2C70F896C6
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Altera_Forum
Honored Contributor II
1,901 Views

 

--- Quote Start ---  

 

Usually altera_modelsim will have these lpm/altera_mf libraries ready from installation. 

 

--- Quote End ---  

 

 

Hi Kaz 

How's about altera_modelsim? 

It's a single software or built-in with quartus software? 

Why I don't see it in my computer? 

Thank you very much.
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Altera_Forum
Honored Contributor II
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Thanks everybody very much. I had already done Modelsim - VHDL. If add 220pack.vhd/220model.vhd in to project and compile it to folder lpm you can work with lpm library in modelsim. Thanks everybody again.

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