Difficulty in Connecting entities in Quartus II

[Altera_Forum]

Hi guys.... 

 Iam a newbie. I entered into FPGA field just 40 days back. Iam using Altera's Quartus II tool for compilation and downloading the code. I have declared two entities differently in separate files. Now I want to connect those two and get the output. The output of entity 1(E1) is going to the input of entity 2(E2).  The declaration of output of E1 is NOT same as that of input of E2. How will I connect those two entities and get the output from E2? Is it necessary to make the block diagram and connect both of them? Is there any other way round? How do I map the output of E1 to input of E2? Remember, both are different files.

[Altera_Forum]

YOu could make a block diag (schematic) and create symbols for each of these, then insert them in to the schematic and provide the interconnections. 

 or  You can write athird file, then 'reference' both of the other two modules (VHDL and Verilog do this differently) and then in this new module, interconnect the two as you desire.  Get a good reference book on multiple file coding, or look at a few examples by others.

[Altera_Forum]

Thanks...the second option that you have given, worked!!!