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Does Cyclone 10 GX general-purpose IO SERDES support diff SSTL-12 output?

Twincreeks
Beginner
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In the post 

https://community.intel.com/t5/Intel-High-Level-Design/Cyclone10-GX-SERDES-using/m-p/1289577/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufEtQV0Y3OTBZN0I0T1NafDEyODk1Nzd8U1VCU0NSSVBUSU9OU3xoSw#M1830

it is stated that

"When using dedicated SERDES circuitry, it does not support differential SSTL IO standard.  The SERDES requires a direct connection to I/O and hence it can only interface to true LVDS I/O. So, please change IO standard of TX pins to LVDS." 

This statement conflicts with table 52 of Intel Cyclone 10 GX Core Fabric and General Purpose I/Os Handbook (https://www.intel.com/content/www/us/en/programmable/documentation/vua1487061384661.html), which explicitly states that SERDES Transmitter I/O Standards Supports diff SSTL-12 (please see the follow screenshot). 

Twincreeks_0-1624484849873.png

Could you please clarify? 

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AminT_Intel
Employee
1,580 Views

Hello,

 

The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

 

Thank you

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4 Replies
AminT_Intel
Employee
1,611 Views

Hello,

 

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Twincreeks
Beginner
1,604 Views

Thank you for your reply.

As you said, the LVDS SERDES IP supports only LVDS. How does Cyclone 10 GX general-purpose support 1.434 Gbps differential SSTL-12 (https://community.intel.com/t5/Programmable-Devices/Does-Cyclone-10-GX-general-purpose-support-1-434-Gbps/m-p/1287593)? I need to transmit 1.434 Gbps data in diff SSTL-12. I cannot use LVDS because the common mode voltage of LVDS is not compatible with the data receiver.  

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AminT_Intel
Employee
1,581 Views

Hello,

 

The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

 

Thank you

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AminT_Intel
Employee
1,564 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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