Downloading ELF failed

[Altera_Forum]

What do I do if I have the error "Downloading ELF failed" in Nios II SBT? 

 I built a system in Qsys that had 0 errors, it compiled and I could load it to the board.   What is then the error in Nios II SBT when I can't load the ELF file?  I tried different run configuration but none of them works.  The processor doesn't seem to respond:  $ nios2-download -g system.elf Using cable "USB-Blaster ", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused

[Altera_Forum]

I am suspecting that the Nios didn't manage to boot up (from the message above). Perhaps you can try a simple Nios design that boots from on-chip memory to confirm this.

[Altera_Forum]

I get the same error with a simple design. First I had to increase the on-chip memory to 64 K.  

 Now I see Nios doesn't start. Maybe I have some design error. How can I know?  $ nios2-download -g /home/developer/proj/quartus0423/software/nios2hello/nios2hello.elf Using cable "USB-Blaster ", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused

[Altera_Forum]

you have to check those. 

 1) reset_n  do you give reset signal to nios?  at least you need to give signal which stuck high.  or a pulse it becomes low once is better.  2)JTAG uart.  if your Qsys does not have JTAG uart.  you have no way to connect with your Qsys.  3) clock.  you certainly need clock after all.  you need double check if the clock is correct.

[Altera_Forum]

Checkout this video and let us know if this helps ... it covers several ways to debug Nios+bare metal systems 

https://www.youtube.com/watch?v=tkvykoowbfe&t=57s&index=40&list=pl0pu5hg9ynizn8vpd1jrnwk6dlauccmdr

[Altera_Forum]

--- Quote Start ---  you have to check those.  1) reset_n  do you give reset signal to nios?  at least you need to give signal which stuck high.  or a pulse it becomes low once is better.  2)JTAG uart.  if your Qsys does not have JTAG uart.  you have no way to connect with your Qsys.  3) clock.  you certainly need clock after all.  you need double check if the clock is correct.  --- Quote End ---    I'm not sure if there is something wrong with my Qsys design.   You may look from the link http://i.imgur.com/l4vag3w.png  It gives no errors in Qsys, it compiles but when I try and run my program it won't start.

[Altera_Forum]

--- Quote Start ---  Checkout this video and let us know if this helps ... it covers several ways to debug Nios+bare metal systems https://www.youtube.com/watch?v=tkvykoowbfe&t=57s&index=40&list=pl0pu5hg9ynizn8vpd1jrnwk6dlauccmdr  --- Quote End ---    Nothing helps. The problem is the debugging. If I get "Downloading ELF failed" then the problem could be anything. That is not a good debugging technique that some specific error could have any cause.   I'm just trying to run a basic C program with the most simple design but no.

[Altera_Forum]

I'm gonna check it. 

 but you still have to check. is your clock(clk_0) working? is you reset_n signal pulled high?  you need to check.

[Altera_Forum]

The Nios II data master is suppose to be connected to AVMM Slave of the jtag uart. Same goes with the timer. 

 You debug_reset_request in your Nios II should be connected to the reset of jtag uart. And disconnect it from the clk_in_reset and nios_ii_gen2_reset.  Refer to this: http://www.alterawiki.com/uploads/4/45/hello_world_lab_manual_max10.pdf and connect the debug_reset_request of nios ii to the jtag_uart_reset.

[Altera_Forum]

Did the project build successfully???

[Altera_Forum]

--- Quote Start ---  The Nios II data master is suppose to be connected to AVMM Slave of the jtag uart. Same goes with the timer.  You debug_reset_request in your Nios II should be connected to the reset of jtag uart. And disconnect it from the clk_in_reset and nios_ii_gen2_reset.  Refer to this: http://www.alterawiki.com/uploads/4/45/hello_world_lab_manual_max10.pdf and connect the debug_reset_request of nios ii to the jtag_uart_reset.  --- Quote End ---    I get an error message in Qsys   Error: system.clk_0: clk_0.clk_in_reset must be connected to a reset source  If I connect it then I get same error again. Nothing works.

[Altera_Forum]

The design looks like this http://i.imgur.com/z93jrly.png 

It compiles. The projects builds. It doesn't work. Fails with "downloading ELF failed".

[Altera_Forum]

Are you running the project after connecting to any DE board. Also after you build the project. Go to quartus compile the project and dump into FPGA. And then comeback to eclipse and select run as hardware.

[Altera_Forum]

Also while you are generating the qsys project. Just have a look in to the files in the pop up where the message appears as generated successfully. Is there nay error or warning as FWD_pointer or something. OR you can go to nios command shell in qsys<tools. Just have a look if this message popups or not.

[Altera_Forum]

--- Quote Start ---  Are you running the project after connecting to any DE board. Also after you build the project. Go to quartus compile the project and dump into FPGA. And then comeback to eclipse and select run as hardware.  --- Quote End ---     Yes I connect it to the DE2-115. I do it right. Nothing works.

[Altera_Forum]

--- Quote Start ---  Also while you are generating the qsys project. Just have a look in to the files in the pop up where the message appears as generated successfully. Is there nay error or warning as FWD_pointer or something. OR you can go to nios command shell in qsys<tools. Just have a look if this message popups or not.  --- Quote End ---    There is no indication that I'm doing anything wrong before the end. And then the error can be anything. Such a debug environment is not good where the error can be anything and waits until the end to generate error msg.

[Altera_Forum]

It wont show the error but as a warning when you are generating the qsys files than see on the box is it showing the warning as something like FWD_pointer.

[Altera_Forum]

Also can you attach the message files you are getting after building the project.

[eamun1]

Is this problem solved? I'm facing the same issue trying different quartus version. 19.1 18. 20.1